Integrated circuit having memory with configurable read/write operations and method therefor
An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin.
1. A method for operating a memory, comprising:
accessing a first portion of the memory, the first portion having a first access margin;
detecting an error in the first portion of the memory;
changing the first access margin to a second access margin, the second access margin being different than the first access margin;
determining that the error is corrected with the first portion having the second access margin; and
storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin.
2. The method of claim 1 , wherein accessing the first portion of the memory further comprises accessing the first portion of the memory for a read operation, and wherein the first and second access margins are first and second read margins.
3. The method of claim 1 , wherein accessing the first portion of the memory further comprises accessing the first portion of the memory for a write operation, and wherein the first and second access margins are first and second write margins.
4. The method of claim 1 , wherein changing the first access margin to the second access margin further comprises changing a magnitude of a power supply voltage provided to the first portion.
5. The method of claim 4 , further comprising comparing the magnitude of the power supply voltage provided to the first portion to a first predetermined threshold, and in response to the magnitude having a predetermined relationship to the first predetermined threshold, changing the first predetermined threshold to a second predetermined threshold.
6. The method of claim 1 , wherein the first portion of the memory comprises a first row of memory cells, and wherein the first row of memory cells is provided with a first power supply voltage during the step of accessing, the first power supply voltage being different than a second power supply voltage provided to a second row of memory cells during the step of accessing.
7. The method of claim 1 , wherein the storing the access assist bit in a first storage element further comprises storing the access assist bit in a location of a status array associated with the memory.
8. The method of claim 1 , wherein detecting the error in the first portion further comprises detecting the error using a built-in self-test (BIST) circuit.
9. The method of claim 1 , wherein the memory is a cache, the cache comprising a plurality of static random access memory (SRAM) cells.
10. A method for accessing a memory comprising:
receiving an access request to a first portion of the memory with a power supply voltage applied to the first portion of the memory at a first value;
detecting an error in the first portion of the memory;
changing the power supply voltage to a second value;
determining that the error is corrected when the power supply voltage is at the second value; and
storing an assist bit in a first storage element, the assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished with the power supply voltage at the second value.
11. The method of claim 10 , wherein the memory access request is a read request, and wherein changing the power supply voltage to the second value further comprises increasing the power supply voltage to the second value in response to reading the assist bit.
12. The method of claim 10 , wherein the memory access request is a write request, and wherein changing the power supply voltage to the second value further comprises decreasing the power supply voltage to the second value in response to reading the assist bit.
13. The method of claim 10 , wherein the memory is a cache memory and the first portion comprises a cache line.
14. The method of claim 10 , wherein storing the assist bit in the first storage element further comprises:
storing a write assist bit for setting the power supply voltage provided to the first portion to a third value during a write operation of the first portion; and
storing a read assist bit for setting the power supply voltage provided to the first portion to a fourth value during a read operation of the first portion.
15. The method of claim 14 , wherein storing the write assist bit further comprises storing the write assist bit in a first location of a status array associated with the first portion and storing the read assist bit further comprises storing the read assist bit in a second location of the status array associated with the first portion.
16. An integrated circuit, comprising:
a processor;
a first memory coupled to the processor, the first memory having an array comprising a plurality of portions of memory cells, each memory cell of the plurality of portions of memory cells having a power supply voltage terminal;
a test circuit coupled to the first memory, the test circuit for testing the first memory and for determining if a failed portion of the first memory is correctable by changing a power supply voltage provided to the failed portion;
an array power supply voltage multiplexer having a first input for receiving a first power supply voltage, a second input for receiving a second power supply voltage, and an output coupled to the power supply voltage terminals of a first portion of the plurality of portions of memory cells; and
a second memory coupled to the array power supply voltage multiplexer, the second memory for storing an access assist bit, the access assist bit associated with the first portion of the plurality of portions of memory cells, the access assist bit being set in response to the test circuit, the access assist bit for determining which one of the first and second power supply voltages is coupled to the power supply voltage terminals of the first portion of the plurality of memory cells during an access of the first portion.
17. The integrated circuit of claim 16 , wherein the first portion is characterized as being a column of memory cells.
18. The integrated circuit of claim 16 , wherein the array power supply voltage multiplexer further comprises a third input for receiving a third power supply voltage, wherein the second memory for storing a second access assist bit, the second access assist bit associated with the first portion, the access assist bit and the second access assist bit for determining which one of the first, second, and third power supply voltages is coupled to the power supply voltage terminals of the first portion during an access of the first portion.
19. The integrated circuit of claim 16 , further comprising:
a threshold voltage register for storing a first plurality of bits corresponding to an access assist threshold voltage; and
a comparator having a first input coupled to receive the first plurality of bits, and a second input coupled to receive a second plurality of bits corresponding to the first power supply voltage, and an output coupled to the array power supply voltage multiplexer, wherein one of the first power supply voltage and the second power supply voltage is provided to the first portion in response to a predetermined comparison result.
20. The integrated circuit of claim 16 , wherein the second memory is characterized as being a status array having a plurality of entries, each of the plurality of entries corresponding to a portion of the plurality of portions of the first memory.