Sense amplifier for semiconductor memory device
View Patent ↗A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
1. A semiconductor memory device comprising:
a plurality of word lines extended in a first direction;
a plurality of bit line pairs extended in a second direction across the first direction;
a plurality of memory cells provided at intersections of the plurality of word lines and the plurality of bit line pairs, wherein each bit line pair includes upper and lower bit lines;
a first local IO line coupled to the plurality of bit line pairs through a sense amplifier column, wherein the sense amplifier column includes a multiplexer circuit receiving first and second selection signals, a first read or write circuit receiving third selection signals, and a transfer gate circuit to couple the sense amplifier column to the upper and lower bit lines;
wherein the plurality of bit line pairs are divided into a plurality of groups of the bit line pairs;
wherein the sense amplifier column selects one of the plurality of groups of the bit line pairs based on the first and second selection signals; and
wherein the sense amplifier column further selects one bit line pair included in the selected one of the plurality of groups of bit line pairs based on the third selection signals to electrically connect with the first local IO line.
2. A semiconductor memory device according to claim 1 ,
wherein the first selection signals and second selection signals extend in the first direction, and
wherein the third selection signals extend in the second direction.
3. A semiconductor memory device according to claim 1 , further comprising:
a plurality of sense amplifiers each coupled between corresponding one of the bit line pairs,
wherein when one of the plurality of word lines is selected, each of the plurality of sense amplifiers amplifies a signal outputted from corresponding two of the plurality of memory cells through corresponding one of the plurality of bit line pairs.
4. A semiconductor memory device according to claim 1 , further comprising:
a second local IO line coupled to the plurality of bit line pairs through the sense amplifier column, wherein the sense amplifier column further includes a second read or write circuit receiving fourth selection signals;
wherein the sense amplifier column selects one of the plurality of groups of the bit line pairs based on the first and second selection signals; and
wherein the sense amplifier column further selects one bit line pair included in the selected one of the plurality of groups of bit line pairs based on the fourth selection signals to electrically connect with the second local IO line,
wherein the first local line transfers a read data and the second local line transfers a write data.
5. A semiconductor memory device according to claim 1 , wherein one of the first read or write circuit and the second read or write circuit includes a plurality of direct sense amplifiers.