Ruthenium interconnect with high aspect ratio and method of fabrication thereof

1. An electronic structure comprising:

a first conductive body, wherein the first conductive body is a silicide layer formed on and in contact with a source/drain of a transistor, a gate oxide and a gate, wherein the gate is a word line of a memory array;

a second conductive body, wherein the second conductive body is a bit line of the memory array;

a dielectric layer between and in contact with the first and second conductive bodies, the dielectric layer defining an opening therethrough, an upper surface of the dielectric layer forming a plane, the second conductive body formed on the upper surface, wherein the dielectric layer comprises a silicon nitride layer;

an adhesion layer within the opening in the dielectric layer; and

an elongated electrically conductive interconnect in the opening providing electrically conductive connection between the first and second conductive bodies, the electrically conductive interconnect comprising ruthenium, wherein the ruthenium entirely fills the opening in the dielectric layer;

wherein the ratio of the length of the electrically conductive interconnect to the minimum cross-sectional width of the electrically conductive interconnect is 20:1 or greater wherein a portion of the first conductive body extends laterally beyond the sides of the ruthenium body and wherein respective portions of the first conductive body do not laterally extend beyond the furthest lateral endpoints of the source/drain of the transistor.

2. The electronic structure of claim 1 , further comprising an electrically conductive interconnect in the opening in the dielectric layer and providing electrically conductive connection between the first and second conductive bodies, the electrically conductive interconnect comprising said adhesion layer and said ruthenium body.

3. The electronic structure of claim 1 wherein the adhesion layer comprises titanium.

4. A method of fabricating an electronic structure comprising:

providing a first conductive body, wherein the first conductive body is a silicide layer formed on and in contact with a source/drain of a transistor, a gate oxide and a gate, wherein the gate is a word line of a memory array;

providing a dielectric layer over and in contact with the first conductive body, an upper surface of the dielectric layer forming a plane, wherein the dielectric layer comprises a silicon nitride layer;

providing an opening through the dielectric layer;

providing an adhesion layer in the opening through the dielectric layer to define a remaining opening;

providing a ruthenium body entirely filling the remaining opening, wherein a ratio of a length of the ruthenium body to a minimum cross-sectional width of the ruthenium body is 20:1 or greater wherein a portion of the first conductive body extends laterally beyond the sides of the ruthenium body and wherein respective portions of the first conductive body do not laterally extend beyond the furthest lateral endpoints of the source/drain of the transistor and wherein the ruthenium body entirely fills the opening in the dielectric layer; and

providing a second conductive body over and in contact with the dielectric layer, the second conductive body formed on the upper surface, wherein the second conductive body is a bit line of the memory array.

5. The method of claim 4 , further comprising providing an electrically conductive interconnect in the opening in the dielectric layer and in contact with the first conductive body and the second conductive body and providing electrically conductive connection between the first and second conductive bodies, the electrically conductive interconnect comprising said adhesion layer and said ruthenium body.

6. The method of claim 4 wherein the adhesion layer comprises titanium.