IP Library Granted Patent US 8,122,599
Granted Patent B2
US 8,122,599 · App. 12/288,740 · Granted Feb 28, 2012

Method of manufacturing a printed circuit board (PCB)

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,122,599
App. No.
12/288,740
Granted
Feb 28, 2012
Kind
B2
Abstract

A printed circuit board (PCB) and appertaining method of manufacturing are provided. The method includes: coating a metal layer on the entire surface of a substrate having an outer surface on which an interconnection pattern is formed; partially removing the metal layer from the surface of the substrate to form a window for a chip to be mounted therein and partially exposing the interconnection pattern to form a bonding finger; forming a first insulating layer on the metal layer by primarily anodizing the metal layer; electroplating a surface of the bonding finger by supplying power to the metal layer; and forming a second insulating layer disposed below the first insulating layer by entirely and secondarily anodizing the metal layer. A gold electroplating process can be performed without a lead wire, and an oxide layer formed by an anodizing process can protect circuits formed on the substrate and electrically insulate them.

Claims (12)

1. A method of manufacturing a printed circuit board (PCB), comprising:

coating a metal layer on an entire surface of a substrate having an outer surface on which an interconnection pattern is formed;

partially removing the metal layer from the surface of the substrate to form a window for a chip to be mounted therein and partially exposing the interconnection pattern to form a bonding finger;

forming a first insulating layer on the metal layer by primarily anodizing the metal layer;

electroplating a surface of the bonding finger by supplying power to the metal layer; and

forming a second insulating layer disposed below the first insulating layer by entirely and secondarily anodizing the metal layer.

2. The method according to claim 1 , wherein the interconnection pattern does not comprise a plating lead wire.

3. The method according to claim 1 , wherein the metal layer is formed of one selected from the group consisting of Al, Mg, Zn, Ti, Ta, Hf, and Nb.

4. The method according to claim 1 , wherein partially exposing the interconnection pattern is performed by an exposure process, a developing process, and an etching process.

5. The method according to claim 1 , wherein electroplating the surface of the bonding finger is performed by a gold electroplating process.

6. The method according to claim 1 , wherein the first and second layers are oxide layers.

7. The method according to claim 1 , wherein the bonding finger is a portion of the interconnection pattern electrically connected to a bonding pad of the chip.

Assignments (3)
CHANGE OF NAME Recorded Apr 16, 2015
From: MDS CO., LTD.
To: HAESUNG DS CO., LTD.
Reel/Frame 035447/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2014
From: SAMSUNG TECHWIN CO., LTD.
To: MDS CO., LTD.
Reel/Frame 032880/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 16, 2009
From: RYU, JAE-CHUL
To: SAMSUNG TECHWIN CO., LTD.
Reel/Frame 022119/0288 →