Semiconductor chip and semiconductor device
A semiconductor chip comprises a semiconductor substrate, a multi-layer wiring structure on the semiconductor substrate, a seal ring structure on the semiconductor substrate, and a semiconductor element arranged in an inner region of said semiconductor chip and in a frame region of said semiconductor chip. The semiconductor element comprises a chip internal circuit, the inner region is enclosed by the seal ling structure, and the seal ring structure separates the frame region as being outside of the inner region.
1 . A semiconductor chip, comprising:
a semiconductor substrate;
a multi-layer wiring structure on the semiconductor substrate, including a seal ring structure on the semiconductor substrate; and
a semiconductor element arranged in an inner region of said semiconductor chip and in a frame region of said semiconductor chip,
wherein the semiconductor element comprises a chip internal circuit element, the inner region is enclosed by the seal ling structure, and the seal ring structure separates the frame region as being outside of the inner region.
2 . The semiconductor chip according to claim 1 , wherein the semiconductor element arranged in the frame region comprises at least one of a metal-oxide semiconductor transistor, a metal-oxide semiconductor capacitor, a diffusion layer resistor, a gate electrode resistor, a silicide resistor, and a diode.
3 . The semiconductor chip according to claim 1 , wherein the semiconductor element arranged in the frame region is covered by at least one of an element protecting film of an upper layer of the semiconductor substrate and the semiconductor substrate, a main layer of interlayer insulating films comprising the multi-layer wiring structure formed on an upper layer of the element protecting film comprises a different material from the element protecting film, and the main layer of the interlayer insulating films comprises a low-dielectric-constant film.
4 . The semiconductor chip according to claim 2 , wherein the semiconductor element arranged in the frame region is covered by at least one of an element protecting film of an upper layer of the semiconductor substrate and the semiconductor substrate, a main layer of interlayer insulating films comprises the multi-layer wiring structure formed on an upper layer of the element protecting film is comprised of a different material from the element protecting film, and the main layer of the interlayer insulating films comprises low-dielectric-constant film.
5 . The semiconductor chip according to claim 3 , wherein the element protecting film comprises one of a single film and a stacked film made from any one of SiO, SiC, SiN, SICN, SiON, and SiN.
6 . The semiconductor chip according to claim 3 , wherein the seal ring structure includes a frame body area and a thinning area, the interlayer insulating film formed by the low-dielectric-constant film is formed in the frame body area, the element protecting film is formed in the thinning area, a conductive layer is formed around the inner region as a frame body and is formed superimposed in a film thickness direction in the frame body area, and the conductive film is formed intermittently in the thinning area.
7 . The semiconductor chip according to claim 5 , wherein the seal ring structure includes a frame body area and a thinning area, the interlayer insulating film formed by the low-dielectric-constant film is formed in the frame body area, the element protecting film is formed in the thinning area, a conductive layer is formed around the inner region as a frame body and is formed superimposed in a film thickness direction in the frame body area, and the conductive film is formed intermittently in the thinning area.
8 . The semiconductor chip according to claim 6 , wherein at least a part of a conductive film in the frame body area and the semiconductor substrate are electrically connected.
9 . The semiconductor chip according to claim 3 , wherein a wiring for connecting the semiconductor element formed in the frame region and the inner region comprises a wiring formed lower than the low-dielectric-constant film.
10 . The semiconductor chip according to claim 5 , wherein a wiring for connecting the semiconductor element formed in the frame region and the inner region comprises a wiring formed lower than the low-dielectric-constant film.
11 . The semiconductor chip according to claim 6 , wherein a wiring for connecting the semiconductor element formed in the frame region and the inner region comprises a wiring formed lower than the low-dielectric-constant film.
12 . The semiconductor chip according to claim 8 , wherein a wiring for connecting the semiconductor element formed in the frame region and the inner region comprises a wiring formed lower than the low-dielectric-constant film.
13 . The semiconductor chip according to claim 9 , wherein the wiring comprises at least one of a diffusion layer, a polycrystalline semiconductor layer, an Aluminum-based wiring, a cupper-based wiring and a silicide wiring.
14 . The semiconductor chip according to claim 1 , wherein the seal ring structure comprises one seal ring structure of a plurality of the seal ring structures, each seal ring structure being formed along an outer periphery of the semiconductor substrate.
15 . The semiconductor chip according to claim 2 , wherein the seal ring structure comprises one seal ring structure of a plurality of the seal ring structures, each seal ring structure being formed along an outer periphery of the semiconductor substrate.
16 . The semiconductor chip according to claim 1 , wherein the semiconductor element comprises one of a plurality of semiconductor elements, wherein a semiconductor element of the plurality of semiconductor elements is respectively arranged at each side of at least two sides configuring the frame region.
17 . The semiconductor chip according to claim 2 , wherein the semiconductor element comprises one of a plurality of semiconductor elements, wherein a semiconductor element of the plurality of semiconductor elements is respectively arranged at each side of at least two sides configuring the frame region.
18 . A semiconductor device comprising:
a semiconductor substrate; and
a semiconductor chip including a multi-layer wiring structure and a seal ring structure on the semiconductor substrate,
wherein the semiconductor chip comprises a semiconductor element arranged in an inner region of the semiconductor chip a frame region of the semiconductor chip, the semiconductor element comprising a chip internal circuit component, the inner region being enclosed to be inside of the seal ring structure, and the frame region is separated as outside of the inner region by the seal ring structure.
19 . The semiconductor device according to claim 18 , wherein the semiconductor element arranged in the frame region comprises at least one of a metal-oxide semiconductor transistor, a metal-oxide semiconductor capacitor, a diffusion layer resistor, a gate electrode resistor, a silicide resistor, and a diode.
20 . The semiconductor device according to claim 18 , wherein the semiconductor element arranged in the frame region is covered by at least one of an element protecting film of an upper layer of the semiconductor substrate and the semiconductor substrate, a main layer of interlayer insulating films comprising the multi-layer wiring structure formed on an upper layer of the element protecting film is comprised of a different material from the element protecting film, and the main layer of the interlayer insulating films comprises a low-dielectric-constant film.
21 . A method of fabricating a semiconductor chip, said method comprising:
forming a semiconductor element on a substrate; and
forming a multi-layer wiring structure on the substrate, including a seal ring structure,
the seal ring structure separates the chip into an inner region enclosed by the seal ring structure and a frame region being outside the seal ring structure, and
the semiconductor element comprises a chip internal circuit component and is located partially in the inner region and partially in the frame region.