Field effect transistor with reduced gate leakage current
View Patent ↗Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of In y Ga 1-y N (0≦y≦1); a carrier supply layer 13 composed of Al x Ga 1-x N (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15 S, a drain electrode 15 D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13 . The following relational expression is satisfied: 5.6×10 11 x<N A ×η×t [cm −2 ]<5.6×10 13 x, where x denotes an Al compositional ratio of the carrier supply layer, t denotes a thickness of the p-type layer, N A denotes an impurity concentration, and η denotes an activation ratio.
1. A field effect transistor comprising:
a channel layer composed of In y Ga 1-y N (0≦y≦1);
a carrier supply layer composed of Al x Ga 1-x N (0≦x≦1), said carrier supply layer being provided over said channel layer and including at least one p-type layer; and
a source electrode, a drain electrode and a gate electrode which are disposed facing said channel layer through said p-type layer, and provided over said carrier supply layer,
wherein the following relational expression is satisfied:
5.6×10 11 x<N A ×η×t [cm −2 ]<5.6×10 13 x, [Mathematical Formula 1]
where x denotes an Al compositional ratio of said carrier supply layer, t denotes a thickness of said p-type layer, N A denotes an impurity concentration of said p-type layer, and η denotes an activation ratio of said p-type layer.
2. The field effect transistor as claimed in claim 1 , wherein said field effect transistor has a negative threshold voltage.
3. The field effect transistor as claimed in claim 1 , wherein said gate electrode is provided on a same plane together with said source electrode and said drain electrode.
4. The field effect transistor as claimed in claim 3 , wherein said field effect transistor has a negative threshold voltage.
5. The field effect transistor as claimed in claim 1 , satisfying the following relational expression:
5.6×10 11 x<N A ×η×t [cm −2 ]<2.8×10 13 x [Mathematical Formula 2].
6. The field effect transistor as claimed in claim 5 , wherein said gate electrode is provided on a same plane together with said source electrode and said drain electrode.
7. The field effect transistor as claimed in claim 5 , wherein said field effect transistor has a negative threshold voltage.
8. A field effect transistor comprising:
a channel layer composed of In y Ga 1-y N (0≦y≦1);
a carrier supply layer composed of Al x Ga 1-x N (0≦x≦1), said carrier supply layer being provided over said channel layer and including at least one p-type layer; and
a source electrode, a drain electrode and a gate electrode which are disposed facing said channel layer through said p-type layer, and provided over said carrier supply layer, said gate electrode being formed to be in contact with a recess portion formed by removing a part of said carrier supply layer,
wherein the following relational expression is satisfied:
5.6×10 11 x<N A ×η×t [cm −2 ]<5.6×10 13 x,
where t denotes a thickness of said p-type layer between said recessed portion and said channel layer, N A denotes an impurity concentration of said p-type layer, and η denotes an activation ratio of said p-type layer.
9. The field effect transistor as claimed in claim 8 , wherein said field effect transistor has a negative threshold voltage.