ESD protection circuit
View Patent ↗The present invention relates a technique using a silicon controlled rectifier (SCR) in a rail based non-breakdown (RBNB) ESD protection device that protects a micro chip from ESD stress. To this end, an ESD protection circuit of the present invention comprises: a detection unit for detecting a rising time of a signal flowing into first and second power lines; a pre-driver for buffering and outputting an output signal of the detection unit; and a power clamp configured with an SCR operating according to the output signal of the pre-driver and connecting the first and second power lines with each other to control current flow between the first and second power lines; wherein the pre-driver includes: first and second MOS transistors respectively having a gate connected to an output terminal of the detection unit and a source connected to the second power line; and a first bipolar transistor respectively having a base connected to a drain of the second MOS transistor and an emitter connected to the first power line.
1. An ESD protection circuit comprising:
a detection unit for detecting a rising time of a signal flowing into first and second power lines;
a pre-driver for buffering and outputting an output signal of the detection unit; and
an SCR operating according to the output signal of the pre-driver and connecting the first and second power lines with each other to control current flow between the first and second power lines;
wherein the pre-driver includes:
first and second MOS transistors respectively having a gate connected to an output terminal of the detection unit and a source connected to the second power line;
and a first bipolar transistor respectively having a base directly connected to a drain of the second MOS transistor and an emitter connected to the first power line.
2. The circuit according to claim 1 , wherein the first and second MOS transistors are an NMOS transistor.
3. The circuit according to claim 1 , wherein the SCR includes:
a second bipolar transistor connected between an output of the first bipolar transistor and the first and second power lines Vdd and Vss; and
a third bipolar transistor connected between an output of the first MOS transistor and the first and second power lines Vdd and Vss.
4. The circuit according to claim 3 , wherein the first and second bipolar transistors are respectively a PNP bipolar transistor, and the third bipolar transistor is an NPN bipolar transistor.
5. The circuit according to claim 1 , wherein the detection unit is configured with an RC filter connected between the first and second power lines in series.