Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device includes: a channel region extending substantially perpendicular to a main surface of a semiconductor substrate; a first diffusion layer provided on a bottom of the channel region; a second diffusion layer provided on a top of the channel region; a first gate electrode that extends substantially perpendicular to the main surface of the semiconductor substrate and that is provided on a side of the channel region through a gate insulation film; and a second gate electrode that extends substantially parallel to the main surface of the semiconductor substrate and that is connected to the top of the first gate electrode, wherein a planar position of the second gate electrode is offset relative to a planar position of the first gate electrode.
1. A semiconductor device, comprising:
a channel region extending substantially perpendicular to a main surface of a semiconductor substrate;
a first diffusion layer provided on a bottom of the channel region;
a second diffusion layer provided on a top of the channel region;
a bottom electrode connected to the first diffusion layer, the bottom electrode being embedded in a cavity within the channel region, along a side thereof;
a first gate electrode that extends substantially perpendicular to the main surface of the semiconductor substrate and that is provided on a side of the channel region through a gate insulation film; and
a second gate electrode that extends substantially parallel to the main surface of the semiconductor substrate and that is connected to the top of the first gate electrode,
wherein a planar position of the second gate electrode is offset relative to a planar position of the first gate electrode.
2. The semiconductor device as claimed in claim 1 , wherein the channel region has first and second sides substantially orthogonal to a direction in which the second gate electrode extends, and
the first gate electrode includes a first portion for covering the first side of the channel region and a second portion for covering the second side of the channel region.
3. The semiconductor device as claimed in claim 2 , wherein the semiconductor substrate has an island-shaped active region protruding in a direction perpendicular to the main surface; and the channel region is formed in the island-shaped active region.
4. The semiconductor device as claimed in claim 3 , wherein the channel region further has third and fourth sides substantially orthogonal to the first and second sides; and
the first gate electrode further includes a third portion for covering the third side of the channel region and a fourth portion for covering the fourth side of the channel region.
5. The semiconductor device as claimed in claim 1 , wherein the semiconductor substrate has a fin-shaped active region intersecting the second gate electrode; and the channel region is formed in the fin-shaped active region.
6. The semiconductor device as claimed in claim 5 , wherein a slit substantially perpendicular to the main surface of the semiconductor substrate is formed in the fin-shaped active region of the semiconductor substrate; and the first gate electrode is embedded in the slit.
7. The semiconductor device as claimed in claim 1 , wherein the bottom electrode that is connected to the first diffusion layer intersects with the second gate electrode.
8. The semiconductor device as claimed in claim 7 , wherein the bottom electrode comprises a first bottom electrode in a first cavity within the channel region, on a first side thereof, the semiconductor device further comprising a second bottom electrode connected to the first diffusion layer, the second bottom electrode being embedded in a cavity within the channel region, along a second side thereof opposite to the first side.
9. The semiconductor device as claimed in claim 1 , further comprising a top electrode connected to a portion that is exposed by the offset of the first gate electrode and the second gate electrode in the second diffusion layer.
10. The semiconductor device as claimed in claim 9 , further comprising a cell capacitor connected to the second diffusion layer through the top electrode.
11. The semiconductor device as claimed in claim 1 , further comprising a dummy gate electrode provided between adjacent second gate electrodes, wherein reverse bias is applied to the dummy gate electrode.