Self-aligned double patterning for memory and other microelectronic devices

1. A method, comprising:

forming a first mask layer and a second mask layer, the second mask layer being on the first mask layer, the first and second mask layers having first and second features, respectively;

at least partially covering the first mask layer and the second mask layer with a film;

forming openings in the film by removing the second feature; and

defining a pattern in a microelectronic layer by patterning the first feature through the openings in the film, wherein forming the first mask layer and the second mask layer includes:

defining the second feature by forming a photoresist mask layer on the second mask layer; and

defining the first feature by forming spacers, wherein each of the spacers includes material that is on a sidewall of the second feature but not directly on top of the second feature, and wherein a height at a highest point of each spacer of the spacers is substantially equal to a combined height of the second mask layer and a photoresist mask layer.

2. The method of claim 1 , wherein forming the first mask layer and the second mask layer includes defining a patterned section of the second mask layer by removing a portion of the second feature via an isotropic etching process.

3. The method of claim 1 , wherein the first feature and the openings of the film define a pitch that has a value that is at least half the value of a minimum pitch of the second mask layer.

4. The method of claim 1 , wherein:

forming the first mask layer and the second mask layer includes depositing the second mask layer on the first layer,

the first mask layer includes the microelectronic layer, and

the second mask layer includes another microelectronic layer.

5. The method of claim 1 , wherein forming the first mask layer and the second mask layer includes forming the first mask layer on the microelectronic layer.

6. The method of claim 1 , wherein at least partially covering the first mask layer and the second mask layer with the film includes depositing a silicon oxide layer.

7. The method of claim 1 , wherein defining the pattern in a microelectronic layer includes defining a pattern associated with at least one of a charge trapping component of a memory ceil, a memory word line, or a memory source gate line.

8. A method of forming a self-aligned structure, comprising:

forming a hard mask and a patterned photoresist mask on the hard mask;

defining combined features in the photoresist mask and the hard mask, wherein the combined features each include a first section and a second section on the first section, wherein the first section includes a portion of the hard mask and the second section includes a portion of the photoresist mask;

forming spacers adjacent to the combined features, wherein each of the spacers is adjacent to the first section and the second section of a corresponding combined feature, wherein each of the spacers includes material that is on a sidewall of the corresponding combined feature but not directly on top of the corresponding combined feature, and wherein a height at a highest point of each spacer of the spacers is substantially equal to a height of the corresponding combined feature; and

patterning a microelectronic layer, including:

employing the spacers to define a first pattern in the microelectronic layer, and

employing at least the first section of the combined features to define a second pattern in the microelectronic layer.

9. The method of claim 8 , wherein each of the spacers has a first width and each first section of the combined features has a second width, and wherein patterning the microelectronic layer further includes defining a pitch of the microelectronic layer that is equal to the first width combined with the second width.

10. The method of claim 8 , wherein the patterning the microelectronic layer includes:

transferring the first pattern into the microelectronic layer by employing the spacers and the first section of the combined features as an etch mask; and

transferring the second pattern in a film positioned on a portion of the hard mask, including:

patterning the film by removing the first section of the combined features; and

employing the patterned film as another etch mask.

11. The method of claim 8 , wherein the microelectronic layer is one of at least two layers of the hard mask, and wherein the patterning the microelectronic layer includes:

etching the first pattern into the microelectronic layer;

removing the spacers from the etched microelectronic layer;

forming a film that at least partially covers the etched microelectronic layer and the first section of the combined features;

removing the first section of the features from the film; and

etching the second pattern into the microelectronic layer through the patterned film.

12. The method of claim 8 , wherein the forming the hard mask and the photoresist mask includes forming a first mask layer on the microelectronic layer and a second mask layer on the first mask layer, wherein each first section of each combined feature includes a portion of the second mask layer.

13. The method of claim 8 , wherein the defining the combined features in the photoresist mask and the hard mask includes performing a timed etch of the hard mask.

14. The method of claim 8 , wherein the defining the combined features in the photoresist mask and the hard mask includes etching the hard mask such that the etch stops at one of at least two layers of the hard mask.

15. A method of forming a self-aligned structure, comprising:

forming a first mask layer and a second mask layer on the first mask layer;

transferring a first pattern into the first mask layer and the second mask layer, wherein the first pattern includes a first feature;

defining a second pattern in the second mask layer by removing a first portion of the first pattern via an isotropic etching process, wherein the first portion is associated with the second mask layer and wherein the second pattern includes a second feature; and

transferring the first pattern and the second pattern into a microelectronic layer,

wherein forming the first mask layer and the second mask layer includes:

defining the second feature by forming a photoresist mask layer on the second mask layer; and

defining the first feature by forming spacers, wherein each of the spacers includes material that is on a sidewall of the second feature but not directly on top of the second feature, and wherein a height at a highest point of each spacer of the spacers is substantially equal to a combined height of the second mask layer and a photoresist mask layer.

16. The method of claim 15 , wherein the first pattern has, at least, a first pitch, and the microelectronic layer has, at least, a second pitch that is less than the first pitch.

17. The method of claim 15 , wherein transferring the first pattern and the second pattern includes:

forming a film that at least partially covers the first mask layer and the second mask layer; and

defining the second pattern in the film by removing the second mask layer.