Phase detector for reducing noise
The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.
1. An delay-lock loop, comprising:
a delay circuit coupled to receive an input clock signal, the delay circuit structured to delay the input clock signal by a delay determined by a delay control signal to provide a delayed clock signal;
a phase detector receiving at least two input signals, the phase detector being structured to determine a phase difference between the at least two input signals and generate at least one output signal based on the determined phase difference, the at least one output signal being used to generate the delay control signal;
a first circuit coupled to receive the at least one output signal from the phase detector, the first circuit being structured to generate a first control signal based upon the at least one output signal; and
a second circuit coupled to receive the input clock signal, the delayed clock signal, and the first control signal, the second circuit being structured to modify at least one of the input clock signal and the delayed clock signal based upon the first control signal to provide a modified signal, the second circuit being structured to provide the modified signal and at least one signal to the phase detector as the at least two input signals to the phase detector, the at least one signal provided to the phase detector being based on at least one of the input clock signal and the delayed clock signal.
2. The delay-lock loop of claim 1 wherein the second circuit is structured to modify the delayed clock signal before providing the modified delayed clock signal to the phase detector.
3. The delay-lock loop of claim 1 wherein the second circuit is structured to modify to modify both the input clock signal and the delayed clock signal and to provide the modified input clock signal and the modified delayed clock signal to the phase detector as the at least two input signals to the phase detector.
4. The delay-lock loop of claim 1 wherein the second circuit comprises a fixed delay circuit and an adjustable delay circuit.
5. The delay-lock loop of claim 1 wherein the phase detector comprises at least one of a latch-type detector, an arbiter-type detector, and a counter-type detector.
6. The delay-lock loop of claim 1 wherein the second circuit comprises a hysteresis adjuster.
7. A delay-lock loop, comprising:
a delay circuit coupled to receive an input clock signal, the delay circuit structured to delay the input clock signal by a delay determined by a delay control signal to provide a delayed clock signal;
a hysteresis circuit coupled to receive the input clock signal and the delayed clock signal, the hysteresis circuit being structured to modify at least one of the input clock signal and the delayed clock signal based upon a phase difference signal to provide a modified signal; and
a phase detector coupled to receive the modified signal from the hysteresis circuit and to receive a signal based on at least one of the input clock signal and the delayed clock signal, the phase detector being structured to determine a difference between a phase of the modified signal and a phase of the signal based on at least one of the input clock signal and the delayed clock signal, the phase detector being structured to provide the difference signal and the delay control signal based on the determined phase difference.
8. The delay-lock loop of claim 7 wherein the hysteresis circuit is structured to modify the delayed clock signal and to then provide the modified delayed clock signal to the phase detector.
9. The delay-lock loop of claim 7 wherein the hysteresis circuit comprises a fixed delay and an adjustable delay.
10. The delay-lock loop of claim 9 wherein the adjustable delay comprises at least two delay elements, at least one of the delay elements in the adjustable delay being selectable based upon the phase difference signal.
11. The delay-lock loop of claim 7 , further comprising a majority filter structured to provide a signal indicative of the desired clock signal delay in response to at least two consecutive difference signals having the same polarity.
12. The difference signal of claim 7 wherein the phase detector comprises at least one of a latch-type detector, an arbiter-type detector, and a counter-type detector.