Semiconductor memory device and operation method thereof
View Patent ↗A semiconductor memory device includes a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal, and a main strobe signal generator configured to generate a main strobe signal by controlling the reference pulse width in response to the reference strobe signal and a bank grouping signal that is activated in a bank grouping mode where columns are continuously accessed in a plurality of logically grouped banks.
1. A semiconductor memory device, comprising:
a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal; and
a main strobe signal generator configured to generate a main strobe signal by controlling the reference pulse width in response to the reference strobe signal and a bank grouping signal that is activated in a bank grouping mode where columns are continuously accessed in a plurality of logically grouped banks.
2. The semiconductor memory device of claim 1 , wherein the main strobe signal has the reference pulse width or an extended pulse width.
3. The semiconductor memory device of claim 1 , wherein the main strobe signal is activated in response to the reference strobe signal and inactivated in response to a reference clock signal.
4. The semiconductor memory device of claim 3 , wherein the main strobe signal generator includes:
an input unit configured to receive the bank grouping signal and the reference clock signal; and
a latch having a first input terminal configured to receive the reference strobe signal and a second input terminal configured to receive an output signal of the input unit and outputting the main strobe signal.
5. The semiconductor memory device of claim 4 , wherein the input unit outputs a signal corresponding to the reference clock signal or a signal having a predetermined logical level in response to the bank grouping signal.
6. The semiconductor memory device of claim 1 , wherein the main strobe signal generator outputs the reference strobe signal as the main strobe signal in response to the bank grouping signal or delays the reference strobe signal by a predetermined time at the time of inactivation of the reference strobe signal and outputs the delayed signal as the main strobe signal.
7. The semiconductor memory device of claim 1 , wherein the bank grouping signal is provided from a mode register set.
8. The semiconductor memory device of claim 1 , further comprising a control signal generator configured to generate a control signal for controlling a circuit related to column access in response to the main strobe signal.
9. A method for driving a semiconductor memory device, comprising:
applying an address corresponding to a bank grouping mode where columns are continuously accessed among a plurality of logically grouped banks;
generating a main strobe signal having a reference pulse width or an extended pulse width in response to the bank grouping mode; and
reading data information corresponding to the address in response to the main strobe signal.
10. The method of claim 9 , wherein generating the main strobe signal includes:
generating a reference strobe signal having the reference pulse width in response to a bank information signal and a column command signal; and
outputting the main strobe signal having an extended reference pulse width in response to the bank grouping mode.
11. The method of claim 10 , wherein the main strobe signal is activated in response to the reference strobe signal and inactivated in response to a reference clock signal.
12. The method of claim 10 , wherein outputting the main strobe signal includes:
outputting a signal corresponding to the reference pulse width in response to the bank grouping signal; and
outputting a signal corresponding to an expanded pulse width in response to the bank grouping signal.
13. The method of claim 10 , wherein the main strobe signal is inactivated after a predetermined time elapsed after an inactivating time of the reference strobe signal.
14. The method of claim 9 , further comprising generating a control signal related to a column access operation in response to the main strobe signal.
15. A semiconductor memory device, comprising:
a reference strobe signal generator configured to generate a reference strobe signal having a reference pulse width in response to a bank information signal and a column command signal; and
a main strobe signal generator configured to output the main strobe signal which has the same pulse width as the reference strobe signal in a non-bank grouping mode and which has more extended pulse width than the reference strobe signal in a bank grouping mode.
16. The semiconductor memory device of claim 15 , wherein the main strobe signal is activated in response to the reference strobe signal and inactivated in response to a reference clock signal.
17. The semiconductor memory device of claim 15 , wherein the bank grouping mode and the non-bank grouping mode are determined by a bank grouping signal provided from a mode register set.
18. The semiconductor memory device of claim 17 , wherein the main strobe signal generator includes:
an input unit configured to receive the bank grouping signal and the reference clock signal; and
a latch having a first input terminal configured to receive the reference strobe signal and a second input terminal configured to receive an output signal of the input unit and outputting the main strobe signal.
19. The semiconductor memory device of claim 18 , wherein the input unit outputs a signal corresponding to the reference clock signal or a signal having a predetermined logical level in response to the bank grouping signal.
20. The semiconductor memory device of claim 15 , further comprising a control signal generator configured to generate a control signal for controlling a circuit related to column access in response to the main strobe signal.