Method for fabricating semiconductor device

1. A method of fabricating a semiconductor device, the method comprising:

etching a semiconductor substrate to form a pillar-type channel region pattern;

forming a buried bit line in a bottom of the channel region pattern;

forming a gate electrode pattern that surrounds the channel region pattern;

forming a word line that connects to the gate electrode pattern;

forming a second interlayer insulating film on the word line, the gate electrode pattern, and the channel region pattern;

etching the second interlayer insulating film using a gate electrode pattern mask;

forming a second gate oxide film in the etched region of the second interlayer insulating film; and

performing an epitaxy process to form a storage node over the channel region pattern and the gate electrode pattern.

2. The method according to claim 1 , further comprising forming a first gate oxide film over the semiconductor substrate and the channel region pattern.

3. The method according to claim 1 , wherein the forming a buried bit line includes:

ion-implanting impurities into the bottom of the channel region pattern;

etching the semiconductor substrate exposed between the channel region patterns using a buried bit line mask; and

forming a first interlayer insulating film over the etched semiconductor substrate.

4. The method according to claim 3 , wherein the forming a first interlayer insulating film includes:

forming an oxide film on sidewalls of the etched semiconductor substrate;

depositing the first interlayer insulating film; and

performing a chemical mechanical polishing (CMP) process to expose a top surface of the channel region pattern.

5. The method according to claim 4 , wherein the forming a first interlayer insulating film includes performing an annealing process before the CMP process to stabilize the first interlayer insulating film.

6. The method according to claim 3 , wherein the forming a gate electrode pattern includes:

etching the first interlayer insulating film using a gate electrode pattern mask to secure a gate region;

depositing a gate electrode material; and

performing a CMP process to expose a top surface of the channel region pattern.

7. The method according to claim 6 , wherein the gate electrode pattern mask exposes a region including an exposed region of a channel region pattern mask that is used to etch the semiconductor substrate to form the channel region pattern.

8. The method according to claim 3 , wherein the forming a word line includes:

etching the first interlayer insulating film exposed by a word line mask;

depositing a word line material; and

performing a CMP process to expose a top surface of the channel region pattern.

9. A method of fabricating a vertical transistor, the method comprising:

forming a pillar-type channel region;

forming a first active region in a bottom of the channel region;

forming a first gate oxide film on sidewalls and a top surface of the channel region;

forming a gate electrode that surrounds the sidewalls of the channel region;

forming a second interlayer insulating film on the gate electrode and the channel region;

etching the second interlayer insulating film using a gate mask;

forming a second gate oxide film over the exposed channel region and the gate electrode; and

depositing silicon over the channel region and the gate electrode by an epitaxy process to form a second active region.

10. The method according to claim 9 , wherein the pillar-type channel region is formed by etching the semiconductor substrate using a channel mask.

11. The method according to claim 9 , further comprising forming a first interlayer insulating film in a region formed by etching the semiconductor substrate so as to separate a vertical transistor from an adjacent vertical transistor.

12. The method according to claim 11 , wherein the gate electrode is formed by filling a gate electrode material in a region formed by etching the first interlayer insulating film that surrounds the channel region using a gate mask.

13. A method of fabricating a semiconductor device, the method comprising:

forming cylindrical channel regions in a semiconductor substrate;

forming an active region in a bottom portion of each channel region;

forming a gate electrode pattern that surrounds upper sidewalls of each channel region;

forming a word line between the gate electrode patterns of adjacent channel regions, wherein the word line connects to the gate electrode patterns;

forming a second interlayer insulating film on the word line, the gate electrode patterns, and the channel regions;

etching the second interlayer insulating film using a gate electrode pattern mask;

forming a second gate oxide film in the etched region of the second interlayer insulating film; and

performing an epitaxy process to form a storage node over each channel region and the corresponding gate electrode pattern.

14. The method according to claim 13 , further comprising forming a first gate oxide film over the semiconductor substrate and the channel region.

15. The method according to claim 13 , wherein the forming an active region includes:

ion-implanting impurities into the bottom portion of each channel region;

etching the semiconductor substrate exposed between the channel regions; and

forming a first interlayer insulating film over the etched semiconductor substrate.

16. The method according to claim 15 , wherein the forming a gate electrode pattern includes :

etching the first interlayer insulating film using a gate electrode pattern mask to secure gate regions;

depositing a gate electrode material; and

performing a CMP process to expose a top surface of each channel region.

17. The method according to claim 15 , wherein the forming a word line includes:

etching the first interlayer insulating film exposed by a word line mask;

depositing a word line material; and

performing a CMP process to expose a top surface of the channel regions.