Memory employing redundant cell array of multi-bit cells
View Patent ↗A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access.
1. A memory, comprising:
a plurality of core cell arrays of multi-bit memory cells;
at least one redundant cell array; and
a memory controller that is configured to dynamically assign the redundant cell array to a failed core cell array of at least a portion of the plurality of core cell arrays when erasing the portion of core cell arrays, wherein the memory controller is further configured to provide access to the redundant cell array when the failed core cell array is selected for read/write access.
2. The memory of claim 1 , further comprising at least one dynamic reference cell array, wherein the memory controller is further configured to identify the failed core cell array by writing a logic state to the dynamic reference cell array.
3. The memory of claim 1 , wherein the core cell arrays and the redundant cell array each include a plurality of dual-bit memory cells.
4. The memory of claim 1 , wherein the plurality of core cell arrays includes at least one of a NOR configuration or a NAND configuration.
5. The memory of claim 1 , wherein the memory controller is further configured to dynamically assign the redundant cell array to another failed core cell array of the plurality of core cell arrays based, at least in part, on under-erase verification.
6. The memory of claim 1 , wherein the memory controller is further configured to soft program the portion of the plurality of core cell arrays, erase the portion of the plurality of core cell arrays, and under-erase verify the portion of the plurality of core cell arrays to identify a failed memory cell of the failed core cell array.
7. The memory of claim 1 , wherein the memory controller is configured to identify the failed core cell array based on one or more threshold voltages of a failed memory cell of the failed core cell array.
8. A memory, comprising:
a plurality of core cell arrays of multi-bit memory cells;
at least one redundant cell array;
a memory controller that is configured to dynamically assign the redundant cell array to a failed core cell array of at least a portion of the plurality of core cell arrays when erasing the portion of core cell arrays, wherein the memory controller is further configured to provide access to the redundant cell array when the failed core cell array is selected for read/write access;
a plurality of dynamic reference cells, wherein each dynamic reference cell of the plurality of dynamic reference cells corresponds to a core cell array of the plurality of core cell arrays;
a plurality of access lines, wherein each core cell array of the plurality of core cell arrays is coupled to at least one access line of the plurality of access lines; and
a plurality of bit lines, wherein each cell of the redundant cell array is coupled to a corresponding core cell of the plurality of core cell arrays via one or more bit lines of the plurality of bit lines.
9. A memory, comprising:
a plurality of core cell arrays of multi-bit memory cells;
at least one redundant cell array;
a memory controller that is configured to dynamically assign the redundant cell array to a failed core cell array of at least a portion of the plurality of core cell arrays when erasing the portion of core cell arrays, wherein the memory controller is further configured to provide access to the redundant cell array when the failed core cell array is selected for read/write access;
a plurality of dynamic reference cells, wherein the memory controller includes one of:
means for addressing the plurality of core cell arrays based, at least in part, on logic states associated with the plurality of dynamic reference cells;
or
means for at least one of reading from or writing to the plurality of core cell arrays and the redundant cell array based, at least in part, on the logic states associated with the plurality of dynamic reference cells.
10. A memory, comprising:
a plurality of cell arrays of multi-bit memory cells, wherein each cell array of the plurality of cell arrays includes at least one dynamic reference cell;
at least one redundant cell array; and
a memory controller coupled to the plurality of cell arrays and the redundant cell array, wherein the memory controller is configured to perform actions, including:
selecting a cell array from the plurality of cell arrays;
reading a dynamic reference cell of the selected cell array;
determining if a logic state of the dynamic reference cell indicates a failure state; and
selecting the redundant cell array and providing read/write access to the redundant cell array based on the logic state.
11. The memory of claim 10 , wherein selecting the redundant cell array includes providing read/write access to the redundant cell array in lieu of read/write access to the selected cell array.
12. The memory of claim 11 , wherein the memory controller actions further include:
erasing the plurality of cell arrays and the redundant cell array;
soft programming at least a portion of the plurality of cell arrays and the redundant cell array; and
identifying a different cell array of the plurality of cell arrays as containing a failed cell based, at least in part, on an under-erase verification.
13. The memory of claim 10 , wherein the memory controller further comprises a decoder circuit, and wherein the memory controller actions further include employing the decoder circuit to select the redundant cell array based on the logic state of the dynamic reference cell.
14. The memory of claim 10 , further comprising a plurality of memory sectors, wherein the plurality of cell arrays is associated with a memory sector of the plurality of memory sectors, and wherein the memory controller actions further include selecting the memory sector.
15. A memory controller, comprising:
a decoder circuit; and
a controller circuit coupled to the decoder circuit, wherein the controller circuit is configured to perform actions, including:
soft-programming a plurality of core cell arrays of multi-bit memory cells;
under-erase verifying each core cell of the plurality of core cell arrays such that if a core cell exceeds a threshold voltage, the core cell array of the failed core cell is identified by writing a logic state to a corresponding dynamic reference cell.
16. The memory controller of claim 15 , wherein the controller circuit actions further include:
pre-programming at least a portion of the core cell arrays; and
erasing the portion of the plurality of the core cell arrays prior to the soft-programming of the plurality of core cell arrays.
17. The memory controller of claim 15 , wherein the controller circuit actions further include identifying a different core cell array during another under-erase verification process by writing a logic state to another dynamic reference cell.
18. The memory controller of claim 15 , wherein writing the logic state to the dynamic reference cell includes writing a logic state to a dual-bit memory cell.
19. The memory controller of claim 15 , wherein the memory controller is configured to read/write at least one of a NOR-based arrayed memory or NAND-based arrayed memory.
20. The memory controller of claim 15 , wherein the decoder circuit is configured to perform actions, including receiving a memory address associated with the core cell array of the failed core cell and decoding the memory address based on the logic state of the dynamic reference cell.