Manufacturing fan-out wafer level packaging

1. A method of manufacturing a fan-out wafer level package, the method comprising:

forming a cavity in a substrate, the cavity having an opening, sidewalls, and a top surface;

affixing double-sided tape to at least a portion of a bottom surface of an integrated circuit, wherein there is a bond pad on a top surface of the integrated circuit;

placing the integrated circuit having the double-sided tape within the opening of the cavity and forming gaps between the sidewalls of the cavity and adjacent sidewalls of the double-sided tape, wherein at least a portion of the double-sided tape contacts at least a portion of the top surface of the cavity in a central region of the cavity, and wherein the sidewalls of the cavity are spaced from the adjacent sidewalls of the double-sided tape;

forming a first dielectric layer that covers substantially all of a top surface of the substrate and that fills the gaps between the sidewalls of the cavity and the adjacent sidewalls of the double-sided tape;

forming a redistribution layer over at least a portion of the first dielectric layer, wherein the redistribution layer is configured to electrically couple the bond pad of the integrated circuit to a redistributed bond pad; and

forming a bump at the redistributed bond pad.

2. The method of claim 1 , wherein affixing the double-sided tape to the bottom surface of the integrated circuit comprises affixing the double-sided tape to the bottom surface of the integrated circuit before placing the integrated circuit within the cavity.

3. The method of claim 1 , wherein the double-sided tape comprises a first adhesive material for affixing to the bottom surface of the integrated circuit and a second adhesive material for affixing to the top surface of the cavity, wherein the double-sided tape comprises a width that is substantially equal to a width of the bottom surface of the integrated circuit.

4. The method of claim 1 , wherein the first dielectric layer includes a bond pad via through which at least a portion of the bond pad is exposed.

5. The method of claim 4 , wherein forming the redistribution layer includes filling at least partially the bond pad via with a portion of the redistribution layer.

6. The method of claim 4 , wherein forming the redistribution layer includes:

sputtering a seed layer over the first dielectric layer and within the bond pad via;

forming a patterned layer over the seed layer using photolithography;

plating at least a portion of the seed layer exposed through the patterned layer to form the redistribution layer;

removing the patterned layer; and

removing at least some of a remaining portion of the seed layer that is not plated.

7. The method of claim 6 , wherein the redistribution layer includes the redistributed bond pad, and wherein forming the bump includes forming the bump in direct contact with the redistribution layer.

8. The method of claim 4 , further comprising forming a second dielectric layer extending at least partially over the redistribution layer, the second dielectric layer including a redistribution via through which at least a portion of the redistribution layer is exposed.

9. The method of claim 8 , further comprising, after forming the second dielectric layer, forming the redistributed bond pad at least partially within the redistribution via.

10. The method of claim 1 , wherein a ratio of a thickness of the substrate to a difference between a width of the cavity and a width of the integrated circuit is greater than or equal to ¼.

11. The method of claim 1 , wherein forming the cavity in the substrate includes stacking layers of substrate material to form the cavity, the stacking comprising forming a first layer of substrate material, forming a second layer of substrate material defining the opening of the cavity, and coupling together the first and second layers of substrate material with at least one adhesive layer interposed therebetween.