Transistor and in-situ fabrication process
View Patent ↗A method of fabricating semiconductor components in-situ and in a continuous integrated sequence includes the steps of providing a single crystal semiconductor substrate, epitaxially growing a first layer of rare earth insulator material on the semiconductor substrate, epitaxially growing a first layer of semiconductor material on the first layer of rare earth insulator material, epitaxially growing a second layer of rare earth insulator material on the first layer of semiconductor material, and epitaxially growing a second layer of semiconductor material on the second layer of rare earth insulator material. The first layer of rare earth insulator material, the first layer of semiconductor material, the second layer of rare earth insulator material, and the second layer of semiconductor material form an in-situ grown structure of overlying layers. The in-situ grown structure is etched to define a semiconductor component and electrical contacts are deposited on the semiconductor component.
1. A semiconductor-on-insulator field effect transistor comprising:
a single crystal silicon substrate;
a buried insulator layer of rare earth insulator material on the semiconductor substrate, the buried insulator layer of rare earth insulator material including a rare earth oxynitride tailored to produce a lattice constant one of larger or smaller than the lattice constant of the silicon substrate, whereby the buried insulator layer forms a strain graded or lattice mismatched pseudo-substrate;
a channel layer of single crystal silicon on the buried insulator layer of rare earth insulator material;
a gate insulator layer of rare earth insulator material on the channel layer;
a gate stack of silicon on the gate insulator layer;
a drain region in the channel layer adjacent one side of the gate stack with a portion of the channel layer in the drain region being doped for conduction;
a source region in the channel layer adjacent an opposite side of the gate stack with a portion of the channel layer in the source region being doped for conduction, the doping in both the drain region and the source region extending through the channel layer to the buried insulator layer to provide a fully depleted channel layer; and
a metal gate contact on the gate stack, a metal drain contact on the doped portion of the channel layer in the drain region, and a metal source contact on the doped portion of the channel layer in the source region.
2. A semiconductor-on-insulator field effect transistor comprising:
a single crystal silicon substrate;
a buried insulator layer of rare earth insulator material on the semiconductor substrate, the buried insulator layer of rare earth insulator material including a rare earth oxynitride tailored to produce a lattice constant one of larger or smaller than the lattice constant of the silicon substrate, whereby the buried insulator layer forms a strain graded or lattice mismatched pseudo-substrate;
a channel layer of single crystal silicon on the buried insulator layer of rare earth insulator material;
a gate insulator layer of rare earth insulator material on the channel layer, the gate insulator layer including a rare earth oxynitride, whereby the rare earth oxynitride layer prevents doping diffusion into the channel layer;
a gate stack of silicon on the gate insulator layer, the silicon stack including doping to provide a selected type of conductance, the gate stack including a layer of rare earth silicide contact material deposited on the silicon;
a drain region in the channel layer adjacent one side of the gate stack with a portion of the channel layer in the drain region being doped for conduction;
a source region in the channel layer adjacent an opposite side of the gate stack with a portion of the channel layer in the source region being doped for conduction, the doping in both the drain region and the source region extending through the channel layer to the buried insulator layer to provide a fully depleted channel layer; and
a metal gate contact on the silicide contact layer of the gate stack, a metal drain contact on the doped portion of the channel layer in the drain region, and a metal source contact on the doped portion of the channel layer in the source region.