Semiconductor device
View Patent ↗A conventional semiconductor device has a problem that, when a vertical PNP transistor as a power semiconductor element is used in a saturation region, a leakage current into a substrate is generated. In a semiconductor device of the present invention, two P type diffusion layers as a collector region are formed around an N type diffusion layer as a base region. One of the P type diffusion layers is formed to have a lower impurity concentration and a narrower diffusion width than the other P type diffusion layer. In this structure, when a vertical PNP transistor is turned on, a region where the former P type diffusion layer is formed mainly serves as a parasite current path. Thus, a parasitic transistor constituted of a substrate, an N type buried layer and a P type buried layer is prevented from turning on, and a leakage current into the substrate is prevented.
1. A semiconductor device comprising an epitaxial semiconductor layer including in which are formed:
a base diffusion layer of one conductivity type,
a base lead diffusion layer of the one conductivity type, formed to overlap the base diffusion layer,
an emitter diffusion layer of an opposite conductivity type, formed to overlap the base diffusion layer, and
a collector diffusion layer of the opposite conductivity type, formed at an upper surface of the epitaxial layer around the base diffusion layer, wherein the collector diffusion layer includes:
a first diffusion layer of the opposite conductivity type extending from the upper surface of the epitaxial layer, and
a second diffusion layer of the opposite conductivity type extending from the upper surface of the epitaxial layer, formed to have a higher impurity concentration than the first diffusion layer,
wherein the first diffusion layer has a region where the first diffusion layer faces the base lead diffusion layer without the emitter diffusion layer therebetween.
2. The semiconductor device according to claim 1 wherein
the second diffusion layer is formed to have a diffusion width wider than the first diffusion layer.
3. The semiconductor device according to any one of claims 1 and 2 wherein
the emitter diffusion layer is disposed between the second diffusion layer and the base lead diffusion layer.
4. The semiconductor device according to any one of claims 1 and 2 , further comprising,
an insulating layer formed on the semiconductor layer; and
a contact hole, formed only in the insulating layer on the second diffusion layer, for connecting a collector electrode to the second diffusion layer.
5. The semiconductor device according to any one of claims 1 and 2 wherein
the base diffusion layer, the base lead diffusion layer and the emitter diffusion layer are each disposed as a pair symmetrical with respect to the second diffusion layer, and
the base lead diffusion layer is disposed farther from the second diffusion layer than the emitter diffusion layer is.
6. The semiconductor device according to any one of claims 1 and 2 wherein
the semiconductor layer further includes,
a diffusion layer of the one conductivity type, formed around the collector diffusion layer,
a buried diffusion layer of the one conductivity type; connected to the diffusion layer of the one conductivity type, and
a buried diffusion layer of the opposite conductivity type, connected to the collector diffusion layer,
the diffusion layer of the one conductivity type is applied with a higher voltage than the collector diffusion layer, and
the buried diffusion layer of the one conductivity type is formed while overlapping the buried diffusion layer of the opposite conductivity type.