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App. No. 12/336,012 · Confirmation No. 1137

METHOD AND APPARATUS OF CIRCUIT SIMULATION OF HIGH-WITHSTAND-VOLTAGE MOS TRANSISTOR

Inventor: Fumitoshi SAITOU
Abandoned -- Failure to Respond to an Office Action View Publication ↗
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2012-02-24 ABN Abandonment 2 View
2011-07-27 CTNF Non-Final Rejection 6 View
2011-07-27 892 List of references cited by examiner 1 View
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2011-07-27 1449 List of References cited by applicant and considered by examiner 1 View
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2011-07-27 SRNT Examiner's search strategy and results 1 View
2009-09-23 EBCC.AD Notice of Change of Address Place in File Wrapper Due to Electronic Business Center(EBC) Customer Number Update 1 View
2009-06-25 NTC.PUB Notice of Publication 1 View
2009-01-26 PD.FILED.E Priority Documents electronically retrieved by USPTO from a participating IP Office 18 View
2009-01-07 APP.FILE.REC Filing Receipt 3 View
2008-12-16 IDS Information Disclosure Statement (IDS) Form (SB08) 1 View
2008-12-16 ABST Abstract 1 View
2008-12-16 ADS Application Data Sheet 3 View
2008-12-16 CLM Claims 5 View
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2008-12-16 TRAN.LET Transmittal Letter 2 View
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2008-12-16 SPEC Specification 16 View
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2008-12-16 WFEE Fee Worksheet (SB06) 1 View
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Quick Facts
App. No.
12/336,012
Filed
2008-12-16
Pub. No.
US20090164196A1
Art Unit
2123