Pad structure of semiconductor integrated circuit apparatus
View Patent ↗A pad structure of a semiconductor integrated circuit apparatus includes a semiconductor substrate upon which circuit patterns forming a device are disposed, a pad disposed on an uppermost part of the semiconductor substrate, and a plurality of fixing parts, each disposed along opposing edge portions of the pad to fix the pad and the semiconductor substrate to each other.
1. A pad structure of a semiconductor integrated circuit apparatus, comprising:
a semiconductor substrate upon which circuit patterns forming a device are disposed;
a pad disposed on an uppermost part of the semiconductor substrate;
a plurality of fixing parts, each disposed along opposing edge portions of the pad to fix the pad and the semiconductor substrate to each other;
a signal line disposed on at least one side of the pad; and
a blocking wire disposed between the signal line and the pad to prevent signal crosstalk.
2. The pad structure of claim 1 , wherein the plurality of fixing parts is disposed between the semiconductor substrate and the pad.
3. The pad structure of claim 2 , wherein each of the plurality of fixing parts includes a contact plug that electrically interconnects the semiconductor substrate and the pad to each other.
4. The pad structure of claim 2 , further comprising an insulating film disposed between the semiconductor substrate and the pad.
5. The pad structure of claim 4 , wherein the contact plug is formed within the insulating film.
6. The pad structure of claim 5 , further comprising a buffer metal pattern array that includes a plurality of buffer metal patterns, each disposed between the semiconductor substrate and the insulating film.
7. The pad structure of claim 6 , wherein each of the plurality of fixing parts is configured to electrically interconnect the buffer metal pattern with the pad.
8. The pad structure claim 1 , wherein the blocking wire includes:
a dummy pattern disposed on substantially the same plane as the buffer metal pattern;
a dummy pad pattern disposed on substantially the same plane as the pad; and
a dummy plug that electrically interconnects the dummy pattern and the dummy pad pattern with each other.
9. The pad structure of claim 1 , wherein the pad has a substantially rectangular structure.
10. The pad structure of claim 9 , wherein each of the plurality of fixing parts is disposed at four corners of the pad.
11. The pad structure of claim 9 , wherein each of the plurality of fixing parts is disposed along two opposing sides of the pad.
12. The pad structure of claim 1 , wherein each of the plurality of fixing parts is disposed along four sides of the pad.
13. A pad structure of a semiconductor integrated circuit apparatus, comprising:
a semiconductor substrate upon which circuit patterns forming a device are disposed;
an insulating film formed on the circuit patterns of the semiconductor substrate;
a pad formed on an upper part of the insulating film and having a substantially rectangular structure;
a buffer metal pattern array disposed between the semiconductor substrate and the insulating film, the buffer metal pattern includes a plurality of buffer metal patterns overlapping the pad;
a plurality of contact plugs disposed along outer side edges of the pad to electrically interconnect and fix the pad and the plurality of buffer metal patterns;
a signal line disposed on at least one side of the pad; and
a blocking wire disposed between the signal line and the pad to prevent signal crosstalk.
14. The pad structure of claim 13 , wherein each of the plurality of contact plugs is disposed at four corners of the pad.
15. The pad structure of claim 13 , wherein each of the plurality of contact plugs is disposed along opposing sides of the pad.
16. The pad structure of claim 13 , wherein each of the plurality of contact plugs is disposed along four sides of the pad.
17. The pad structure of claim 13 , wherein the blocking wire includes:
a dummy pattern disposed on substantially the same plane as the buffer metal pattern;
a dummy pad pattern disposed on substantially the same plane as the pad; and
a dummy plug electrically interconnecting the dummy pattern and the dummy pad pattern with each other.