Granted Patent B2

US 8,352,818 · App. 12/336,472 · Granted Jan 8, 2013

Abstract

Claims (40)

1. A method of generating a test pattern set for detecting small delay defects of an integrated circuit, comprising:

generating traditional delay fault patterns;

fault grading said traditional delay fault patterns for small delay defect coverage;

reporting faults detected by said fault grading and delay information associated with said detected faults;

determining which of said detected faults are timing-aware target faults employing said delay information;

generating timing-aware delay fault patterns for said timing-aware target faults; and

combining said traditional delay fault patterns and said timing-aware delay patterns to provide a small delay defect targeted pattern set.

2. The method as recited in claim 1 wherein said traditional delay fault patterns are transition delay fault patterns.

3. The method as recited in claim 1 wherein said traditional delay fault patterns are in-line resistive fault patterns.

4. The method as recited in claim 1 wherein said delay information includes maximum static slack.

5. The method as recited in claim 4 wherein said fault grading includes selecting a path of said integrated circuit for applying said traditional delay fault patterns, said delay information including a slack of said selected path.

6. The method as recited in claim 5 wherein said determining a timing-aware target fault includes determining if said slack of said selected path is greater than a designated slack margin.

7. The method as recited in claim 1 further comprising determining which of said detected faults are non-timing aware target faults.

8. The method as recited in claim 7 further comprising fault grading said timing-aware delay fault patterns on said non-timing aware target faults.

9. The method as recited in claim 8 further comprising generating delay fault patterns for faults undetected by said fault grading on said non-timing aware target faults.

10. The method as recited in claim 9 further comprising combining said delay fault patterns and said timing-aware delay fault patterns to provide an alternative small delay defect targeted pattern set.

11. A method of generating a test pattern set for detecting small delay defects of an integrated circuit, comprising:

filtering faults detected by fault grading traditional delay fault patterns for small delay defect coverage to determine which of said detected faults are timing-aware target faults;

generating timing-aware delay fault patterns only for said timing-aware target faults; and

combining said traditional delay fault patterns and said timing-aware delay patterns to provide a small delay defect targeted pattern set.

12. The method as recited in claim 11 wherein said traditional delay fault patterns are transition delay fault patterns.

13. The method as recited in claim 11 wherein said traditional delay fault patterns are in-line resistive fault patterns.

14. The method as recited in claim 11 wherein said filtering includes employing timing information associated with said detected faults to determine which of said detected faults are timing-aware target faults.

15. The method as recited in claim 14 wherein said timing information includes maximum static slack.

16. The method as recited in claim 15 wherein said timing information includes a slack of a path selected for applying said traditional delay fault patterns.

17. The method as recited in claim 16 wherein said filtering includes determining if said slack of said selected path is greater than a designated slack margin.

18. The method as recited in claim 11 wherein said filtering further determines which of said detected faults are non-timing aware target faults.

19. The method as recited in claim 18 further comprising fault grading said timing-aware delay fault patterns on said non-timing aware target faults and generating delay fault patterns for faults undetected by said fault grading on said non-timing aware target faults.

20. The method as recited in claim 19 further comprising combining said delay fault patterns and said timing-aware delay fault patterns to provide an alternative small delay defect targeted pattern set.

21. A test pattern generator embodied as a plurality of instructions on a computer-readable storage medium that when said plurality of instructions are executed by a processor cause said processor to create a test pattern set for detecting small delay defects of an integrated circuit, said test pattern generator comprising:

a fault filter configured to filter faults detected by fault grading traditional delay fault patterns for small delay defect coverage to determine which of said detected faults are timing-aware target faults;

a fault pattern generator configured to generate timing-aware delay fault patterns only for said timing-aware target faults; and

a pattern combiner configured to combine said traditional delay fault patterns and said timing-aware delay fault patterns to provide a small delay defect targeted pattern set.

22. An apparatus for detecting small delay defects of an integrated circuit, comprising:

circuitry for generating traditional delay fault patterns;

circuitry for fault grading said traditional delay fault pattern for small delay defect coverage;

circuitry for reporting faults detected by said fault grading and delay information associated with said detected faults;

circuitry for determining which of said detected faults are timing-aware target faults employing said delay information;

circuitry for generating timing-aware delay fault patterns for said timing-aware target faults; and

circuitry for combining said traditional delay fault patterns and said timing-aware delay patterns to provide a small delay defect targeted pattern set.

Assignments (9)