Granted Patent B2

US 8,423,942 · App. 12/339,407 · Granted Apr 16, 2013

Abstract

Claims (42)

1. A fill-placement method, comprising:

selecting a die area corresponding to symmetrical circuitry;

identifying two or more symmetrical portions within the selected die area;

generating a seed fill pattern for a first of the identified symmetrical portions, said seed fill pattern formed by a plurality of fill tiles positioned between conducting tracks; and

replicating the seed fill pattern to generate a replicated fill pattern for at least one of the remaining one or more of the identified symmetrical portions, wherein:

the seed fill pattern and a first replicated fill pattern are related through a first mirror reflection;

the seed fill pattern and a second replicated fill pattern are related through a second mirror reflection that is different from the first mirror reflection; and

each of the first and second mirror reflections is defined by a respective symmetry plane, with the two symmetry planes being orthogonal to each other.

2. The method of claim 1 , wherein the symmetrical circuitry comprises a plurality of complementary opposite circuit elements.

3. The method of claim 1 , wherein the step of identifying comprises selecting an interconnect level of the selected die area, wherein the first symmetrical portion and a second of the identified symmetrical portions are both parts of the selected interconnect level.

4. The method of claim 1 , wherein:

the selected die area comprises at least first and second interconnect levels;

two or more of the identified symmetrical portions that are parts of the first interconnect level are related by a first symmetry operation; and

two or more of the identified symmetrical portions that are parts of the second interconnect level are related by a second symmetry operation that is different from the first symmetry operation.

5. The method of claim 1 , further comprising sorting conducting tracks of a plurality of interconnect levels in the selected die area into at least first and second categories, wherein the step of generating comprises, within a specified keep-out depth, avoiding placing fill tiles directly below and directly above the conducting tracks that have been sorted into the first category.

6. The method of claim 5 , wherein the step of generating further comprises placing fill tiles at one or both of (i) directly below and (ii) directly above the conducting tracks that have been sorted into the second category.

7. The method of claim 6 , wherein the second category includes conducting tracks that carry power-supply signals.

8. The method of claim 5 , wherein the specified keep-out depth is greater than one interconnect level.

9. A plurality of fill-placement patterns for a corresponding plurality of interconnect levels of an integrated circuit, said plurality of fill-placement patterns generated by implementing on a computer the method of claim 1 .

10. An integrated circuit having a plurality of interconnect levels, each having a respective fill-placement pattern, wherein at least one of said fill-placement patterns has been generated by implementing on a computer the method of claim 1 .

11. A non-transitory machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements the method of claim 1 .

12. The method of claim 1 , wherein:

the fill tiles are to be implemented using a metal; and

at least some fill tiles of the plurality are configured to be electrically floating.

13. A fill-placement method, comprising:

selecting a die area corresponding to symmetrical circuitry;

identifying two or more symmetrical portions within the selected die area;

generating a seed fill pattern for a first of the identified symmetrical portions;

replicating the seed fill pattern to generate a replicated fill pattern for at least one of the remaining one or more of the identified symmetrical portions; and

sorting conducting tracks of a plurality of interconnect levels in the selected die area into at least first and second categories, wherein the step of generating comprises, within a specified keep-out depth, avoiding placing fill tiles directly below and directly above the conducting tracks that have been sorted into the first category.

14. The method of claim 13 , wherein the step of generating further comprises placing fill tiles at one or both of (i) directly below and (ii) directly above the conducting tracks that have been sorted into the second category.

15. The method of claim 14 , wherein the second category includes conducting tracks that carry power-supply signals.

16. The method of claim 13 , wherein the specified keep-out depth is greater than one interconnect level.

17. A fill-placement method, comprising:

selecting a die area corresponding to symmetrical circuitry;

identifying two or more symmetrical portions within the selected die area;

generating a seed fill pattern for a first of the identified symmetrical portions; and

replicating the seed fill pattern to generate a replicated fill pattern for at least one of the remaining one or more of the identified symmetrical portions, wherein:

the seed fill pattern and the replicated fill pattern are related via a rotation operation with respect to a rotation axis; or

the seed fill pattern and the replicated fill pattern are related via a translation operation; or

a first replicated fill pattern and a second replicated fill pattern are related to the seed fill pattern via a first mirror reflection and via a second mirror reflection, respectively, wherein each of the first and second mirror reflections is defined by a respective symmetry plane, with the two symmetry planes being orthogonal to each other; or

a first replicated fill pattern and a second replicated fill pattern are related to the seed fill pattern via a mirror reflection and via an inversion operation with respect to an inversion axis, respectively.

Assignments (10)