Level shift circuit
View Patent ↗An amplifier including the transistors of a first set operates by a power source VCC 2 , and amplifies the input signal, changing in the voltage range of the power source VCC 2 , in the voltage range of the power source VCC 2 . The output of this amplifier operates using a power source VCC 1 with a converting portion including the transistors of a second set, and the output of the amplifier is converted into an output within the voltage range of the power source VCC 1 . The two output amplifiers amplify the output of this converting portion based on a (½) VCC 1 reference. The converting portion performs the conversion using a plurality of transistors with the power source VCC 2 taken as a power source and a plurality of transistors 7 with the power source VCC 1 taken as a power source, as current mirrors.
1. A level shift amplifier circuit for amplifying and level-shifting an input signal, comprising:
an input side amplifier configured to amplify the input signal to generate an amplified input signal; and
a converting circuit configured to convert the amplified input signal to a pair of converted output signals;
wherein the input side amplifier is configured to operate from a second power source voltage,
wherein the converting circuit comprises a current mirror circuit that comprises an input side transistor configured to operate from the second power source voltage and an output side transistor configured to operate from a first power source voltage,
wherein a voltage range of the input signal and the amplified input signal are within a voltage range of the second power source voltage, and
wherein a voltage range of the converted output signals is within a voltage range of the first power source voltage.
2. The level shift amplifier circuit according to claim 1 , further comprising: an output side amplifier for amplifying the pair of converted output signals by a voltage reference of half the first power source voltage.
3. A level shift circuit, comprising:
a first transistor of a p type receiving an input signal at a control terminal and configured such that a current I 1 corresponding to a control signal flows;
a first fixed current circuit configured such that a fixed current I 0 flows from a second power source toward the first transistor;
a second transistor of a p type receiving a reference signal at the control terminal and configured such that a current I 2 corresponding to the reference signal flows;
a second fixed current circuit configured such that the fixed current I 0 flows from the second power source toward the second transistor;
a third transistor of an n type receiving an input signal at the control terminal and configured such that the current flows from the second power source;
a third fixed current circuit configured such that a fixed current I 0 flows from the third transistor to ground;
a fourth transistor of an n type receiving the reference signal at the control terminal and configured such that the current to flow from the second power source;
a fourth fixed current circuit configured such that fixed current I 0 flows from the fourth transistor toward ground;
a first resistor, having one end connected to an upstream side of the first transistor and the other end connected to a downstream side of the fourth transistor such that current I 0 -I 1 flows; and
a second resistor, having one end connected to an upstream side of the second transistor and the other end connected to a downstream side of the third transistor, such that current I 0 -I 2 flows;
wherein the currents flowing through the first transistor and the third transistor are respectively converted into current with a first power source as a reference by using a current mirror, and by adding these currents, a difference signal thereof is obtained, and
wherein the currents flowing through the second transistor and the fourth transistor are respectively converted into current with the first power source as a reference by using a current mirror, and by adding these currents, a difference signal thereof is obtained, and
wherein the two difference signals thus obtained are outputted as in-phase and reverse-phase signals.
4. The shift level circuit according to claim 3 , further comprising two amplifiers for respectively amplifying the two difference signals with the first power source as a reference, and wherein a pair of complementary signals are outputted from these two amplifiers.