IP Library Granted Patent US 8,097,961
Granted Patent B2
US 8,097,961 · App. 12/341,863 · Granted Jan 17, 2012

Semiconductor device having a simplified stack and method for manufacturing thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,097,961
App. No.
12/341,863
Granted
Jan 17, 2012
Kind
B2
Abstract

Embodiments of the present invention are directed to provide a semiconductor device including a semiconductor chip formed of a conductive material, a connector terminal around the semiconductor chip, which is formed of a same material for forming the semiconductor chip, an insulating member for electrically insulating the semiconductor chip from the connector terminal, and a first connection member for electrically coupling the semiconductor chip with the connector terminal. Simplified step of manufacturing the connector terminal may further simplify the steps of manufacturing the semiconductor device.

Claims (29)

1. A semiconductor device comprising:

a semiconductor chip formed of conductive silicon;

a connector terminal formed of the same material as is the semiconductor chip, wherein the connector terminal is disposed around the semiconductor chip;

an insulating member for electrically insulating the semiconductor chip from the connector terminal; and

a first connection member for electrically coupling the semiconductor chip with the connector terminal,

wherein the semiconductor device is formed by electrically insulating the semiconductor chip from the connector terminal via the insulating member, and electrically coupling the semiconductor chip with the connector terminal via the first connection member.

2. The semiconductor device according to claim 1 , wherein the insulating member covers a plurality of side surfaces of the semiconductor chip and the connector terminal.

3. The semiconductor device according to claim 2 , wherein the plurality of side surfaces of the semiconductor chip and the connector terminal are covered by the insulating member such that the semiconductor chip and the connector terminal are not in direct contact with each other.

4. The semiconductor device according to claim 1 , wherein a plurality of connector terminals is arranged along at least one side of the semiconductor chip.

5. The semiconductor device according to claim 4 , wherein the insulating member covers a plurality of side surfaces of the plurality of connector terminals so as to prevent the plurality of connector terminals from being in direct contact with one another.

6. The semiconductor device according to claim 1 , wherein;

the connector terminal comprises a surface covered with a metal layer; and

the connection member is electrically coupled with the connector terminal via the metal layer.

7. The semiconductor device according to claim 1 , wherein each of the semiconductor chip and the connector terminal comprises a conductive silicon material.

8. The semiconductor device according to claim 1 , wherein the connection member comprises a redistribution layer.

9. The semiconductor device according to claim 1 , wherein the connection member comprises a bonding wire.

10. A stack type semiconductor device comprising a plurality of stacked semiconductor devices, the plurality of stacked semiconductors comprising:

a first semiconductor device comprising a first semiconductor chip, a first connector terminal disposed around the first semiconductor chip, a first insulating member for electrically insulating the semiconductor chip from the connector terminal and a first connection member for electrically coupling the semiconductor chip with the first connector terminal wherein the first connector terminal and the first semiconductor device are formed from the same material and wherein that material is conductive silicon; and

a second semiconductor device comprising a second semiconductor chip, a second connector terminal disposed around the second semiconductor chip, a second insulating member for electrically insulating the semiconductor chip from the second connector terminal and a second connection member for electrically coupling the semiconductor chip with the second connector terminal;

wherein a first surface of the first connector terminal is electrically coupled with a second surface of the second connector terminal.

11. The stack type semiconductor device of claim 10 , wherein

the plurality of stacked semiconductors comprises a plurality of vertically stacked semiconductors; and

the first semiconductor device is vertically adjacent to the second semiconductor device.

12. The stack type semiconductor device of claim 10 , wherein the first surface of the first connector terminal is a side surface of the first connector terminal.

13. The stack type semiconductor device of claim 12 , wherein the second surface of the second connector terminal is a side surface of the second connector terminal.

14. The stack type semiconductor device of claim 10 , wherein:

the first semiconductor device is stacked on top of the second semiconductor device; and the first surface of the first connector terminal comprises a lower surface of the first connector terminal.

15. The stack type semiconductor device of claim 14 , wherein the second

surface of the second connector terminal comprises an upper surface of the second connector terminal.

Assignments (9)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2025
From: MONTEREY RESEARCH LLC
To: SOUTHFORK IP HOLDINGS LLC
Reel/Frame 071299/0161 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036051/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2009
From: TANAKA, JUNJI; TAYA, KOJI; HARAYAMA, MASAHIKO
To: SPANSION LLC
Reel/Frame 022250/0221 →