Time reduction of address setup/hold time for semiconductor memory
View Patent ↗In the storage device of the invention, latch control is performed on a series of signals in response to latch control signals. Latch control terminals are provided to which the latch control signals are input respectively and a plurality of signal terminals to which a series of signals are input. Herein, a plurality of latch circuits is provided so as to correspond to the plurality of signal terminals, respectively. The plurality of latch circuits are located within a specified distance from their associated signal terminals respectively and within a specified distance from the latch control terminals. The delays of signal transmission from the signal terminals to their associated latch circuits can be equalized and the delays of signal transmission from the latch control terminals to which the latch control signals for executing latch control are input to the latch circuits can be equalized. This contributes to a reduction in the skew of the latch characteristics of the signals.
1. A storage device comprising:
latch control terminals to which latch control signals for performing latch control on a series of signals are input;
a plurality of signal terminals to which the series of signals is input;
a plurality of latch circuits which are provided so as to correspond to the plurality of signal terminals, the plurality of latch circuits being located at such positions that distances from the plurality of signal terminals to their associated latch circuits do not exceed a specified range and distances from the latch control terminals to their associated latch circuits do not exceed a specified range; and
a latch control circuit connected to the latch control terminals to which the latch control signals are input, the latch control circuit outputting a latch signal to the latch circuit; wherein the specified ranges from the signal terminals to the latch circuit are not longer than a distance with which delays of transmission by the signal lines from the signal terminals to the latch circuit become the maximum allowable transmission delay; and the specified ranges from the latch control terminals to the latch circuit are not longer than a distance with which delay of transmission after a latch control signal is input to each latch control terminal until it is transmitted as a latch signal to the latch circuit through the latch control circuit becomes the maximum allowable transmission delay.
2. The storage device according to claim 1 , wherein the plurality of signal terminals, having a common region that is located within the specified range from each of the signal terminals, constitute a terminal group; and where the latch control terminals are so positioned in relation to the terminal group that at least a part of a region that is located within the specified range from the latch control terminal overlaps at least a part of the common region.
3. The storage device according to claim 1 , wherein latch control signals for latching a signal group vary from operation mode to operation mode.
4. The storage device according to claim 2 , wherein the signal terminals are divided into two terminal groups.
5. The storage device according to claim 1 , wherein the series of signals are address signals.
6. The storage device according to claim 1 , wherein the series of signals are data signals.
7. The storage device according to claim 1 , wherein the series of signals are address signals and data signals.
8. The storage device according to claim 2 , wherein the series of signals are address signals.
9. The storage device according to claim 2 , wherein the series of signals are data signals.
10. The storage device according to claim 2 , wherein the series of signals are address signals and data signals.
11. A storage device comprising:
latch control terminals to which latch control signals for performing latch control on a series of signals are input;
a plurality of signal terminals to which the series of signals is input;
a plurality of latch circuits which are provided so as to correspond to the plurality of signal terminals, the plurality of latch circuits being located at such positions that distances from the plurality of signal terminals to their associated latch circuits do not exceed a specified range and distances from the latch control terminals to their associated latch circuits do not exceed a specified range;
the plurality of signal terminals, having a common region that is located within the specified range from each of the signal terminals, constitute a terminal group; and
where the latch control terminals are so positioned in relation to the terminal group that at least a part of a region that is located within the specified range from the latch control terminal overlaps at least a part of the common region; and
a latch control circuit connected to the latch control terminals to which the latch control signals are input, the latch control circuit outputting a latch signal to the latch circuit; wherein the specified ranges from the signal terminals to the latch circuit are not longer than a distance with which delays of transmission by the signal lines from the signal terminals to the latch circuit become the maximum allowable transmission delay; and the specified ranges from the latch control terminals to the latch circuit are not longer than a distance with which delay of transmission after a latch control signal is input to each latch control terminal until it is transmitted as a latch signal to the latch circuit through the latch control circuit becomes the maximum allowable transmission delay.
12. The storage device according to claim 11 , wherein the signal terminals are divided into two terminal groups.
13. The storage device according to claim 11 , wherein latch control signals for latching a signal group vary from operation mode to operation mode.
14. The storage device according to claim 11 , wherein the series of signals are address signals.
15. The storage device according to claim 11 , wherein the series of signals are data signals.
16. The storage device according to claim 11 , wherein the series of signals are address signals and data signals.