XOR logic circuit

1. An XOR logic circuit, comprising:

a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals;

a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the second input terminal; and

a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first input terminal.

2. The XOR logic circuit of claim 1 , wherein the first transfer unit includes a plurality of MOS transistors that are cross-coupled.

3. The XOR logic circuit of claim 1 , wherein the first transfer unit includes:

a first PMOS transistor configured to have a source-drain path formed between the first input terminal and the output terminal and a gate coupled to the second input terminal; and

a second PMOS transistor configured to have a source-drain path formed between the second input terminal and the output terminal and a gate coupled to the first input terminal.

4. The XOR logic circuit of claim 1 , wherein the multiplexing unit includes:

a first output unit configured to output the power voltage in

response to the data applied to the second input terminal; and

a second output unit configured to output the ground voltage in response to the data applied to the second input terminal,

wherein the first and second output units output the power voltage and the ground voltage through a common node, respectively.

5. The XOR logic circuit of claim 4 , wherein the first output unit includes:

a PMOS transistor configured to have a source-drain path coupled between the power voltage terminal and the common node, and a gate coupled to the second input terminal; and

an NMOS transistor configured to have a source-drain path coupled between the ground voltage terminal and the common node, and a gate coupled to the second input terminal.

6. The XOR logic circuit of claim 1 , wherein the second transfer unit includes:

a first NMOS transistor configured to have a source-drain formed between the output terminal and the first input terminal, and a gate coupled to the output terminal of the multiplexing unit; and

a second NMOS transistor configured to have a source-drain formed between the output terminal and an output terminal of the multiplexing unit and a gate coupled to the first input terminal.

7. The XOR logic circuit of claim 1 , wherein a sub path for performing a sub differential operation for the output terminal is formed on the second transfer unit in response to a main path being formed on the first transfer unit to transfer the logic high level data to the output terminal.

8. The XOR logic circuit of claim 1 , wherein a sub path for performing a sub discharging operation for the output terminal is formed on the first transfer unit in response to a main path being formed on the second transfer unit to transfer the logic low level data to the output terminal.

9. The XOR logic circuit of claim 1 , wherein the multiplexing unit one of controls the second transfer unit based on the data and applies the logic low level data to the second transfer unit.

10. The XOR logic circuit of claim 1 , wherein the first transfer unit is configured to receive the data having a different polarity applied to the first and second input terminals, and the second transfer unit is configured to receive the data having the same polarity applied to the first and second input terminals.

11. An XOR logic circuit, comprising:

a first PMOS transistor configured to have a source-drain path formed between a first input terminal and an output terminal and a gate coupled to a second input terminal;

a second PMOS transistor configured to have a source-drain path formed between the second input terminal and the output terminal and a gate coupled to the first input terminal;

a first NMOS transistor configured to have a source-drain path formed between the output terminal and the first input terminal and a gate coupled to a common node;

a second NMOS transistor configured to have a source-drain path formed between the output terminal and the common node and a gate coupled to the first input terminal;

a third PMOS transistor configured to have a source-drain path formed between a power voltage terminal and the common node and a gate coupled to the second input terminal; and

a third NMOS transistor configured to have a source-drain path formed between a ground voltage terminal and the common node and a gate coupled to the second input terminal.

12. The XOR logic circuit of claim 11 , wherein the first PMOS transistor has a main path for transferring the logic high level data to the output terminal in response to a logic high level data being applied to the first input terminal and a logic low level data being applied to the second input terminal.

13. The XOR logic circuit of claim 11 , wherein the second NMOS transistor and the third PMOS transistor have a sub path for performing a sub charging operation at the output terminal in response to a logic high level data being applied to the first input terminal and a logic low level data being applied to the second input terminal.

14. The XOR logic circuit of claim 11 , wherein the second PMOS transistor has a main path for transferring the logic high level data to the output terminal in response to a logic low level data being applied to the first input terminal and a logic high level data being applied to the second input terminal.

15. The XOR logic circuit of claim 11 , wherein the first NMOS transistor has a main path for transferring the logic low level data to the output terminal in response to a logic low level data being applied to the first input terminal and a logic low level data being applied to the second input terminal.

16. The XOR logic circuit of claim 11 , wherein the first PMOS transistor and the second PMOS transistor have a sub path for performing a sub discharging operation at the output terminal in response to a logic low level data being applied to the first input terminal and a logic low level data being applied to the second input terminal.

17. The XOR logic circuit of claim 11 , wherein the second NMOS transistor and the third NMOS transistor have a main path for transferring the logic low level data to the output terminal in response to a logic high level data being applied to the first input terminal and a logic high level data being applied to the second input terminal.

18. The XOR logic circuit of claim 11 , wherein the first NMOS transistor is controlled by the data applied to the second input terminal.