Semiconductor memory apparatus
View Patent ↗A semiconductor memory apparatus includes first and second bank blocks, a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks, and a controller configured to drive the first and second bank blocks in response to the chip select mode signal, first and second select signals, and a predetermined address signal that are used to control driving of the first and second bank blocks, wherein the controller receives the chip select mode signal having a level used to determine a single chip mode to control operation of the first and second bank blocks in one rank unit, and the first and second bank blocks are selectively activated by using the predetermined address signal.
1. A semiconductor memory apparatus, comprising:
first and second bank blocks;
a mode generator configured to generate a chip select mode signal used to control an operational mode of the first and second bank blocks; and
a controller configured to drive the first and second bank blocks in response to the chip select mode signal, first and second select signals, and a predetermined address signal that are used to control driving of the first and second bank blocks,
wherein the controller receives the chip select mode signal having a level used to determine a single chip mode to control operation of the first and second bank blocks in one rank unit, and the first and second bank blocks are selectively activated by using the predetermined address signal.
2. The semiconductor memory apparatus of claim 1 , wherein the predetermined address signal is excluded in designation of a memory cell in the first and second bank blocks.
3. The semiconductor memory apparatus of claim 1 , wherein the controller selectively controls the driving of the first and second bank blocks in response to a level of the predetermined address signal even if both of the first and second chip select signals are activated.
4. A semiconductor memory apparatus, comprising:
first and second bank blocks, each including a plurality of banks;
a mode generator configured to generate a bank mode signal and a chip select mode signal to control an operational mode; and
a controller configured to control activation of the first and second bank blocks according to a level of first and second chip select signals when the chip select mode signal is activated, to control the activation of the first and second bank blocks by using a predetermined address signal if the chip select mode signal is deactivated, and to selectively control precharge of the first and second bank blocks in response to the bank mode signal in a precharge mode.
5. The semiconductor memory apparatus of claim 4 , wherein the predetermined address signal is excluded in designation of a memory cell in the first and second bank blocks.
6. The semiconductor memory apparatus of claim 4 , wherein the controller selectively controls activation of the first and second bank blocks in response to a level of the predetermined address signal even if both of the first and second chip select signals are activated.
7. The semiconductor memory apparatus of claim 4 , wherein the first and second bank blocks operate in response to a same column command according to the predetermined address signal if the chip select mode signal has a first level.
8. The semiconductor memory apparatus of claim 7 , wherein the first and second bank blocks operate in response to column commands applied to the first and second bank blocks regardless of the predetermined address signal if the chip select mode signal has a second level.
9. The semiconductor memory apparatus of claim 4 , wherein the controller includes:
a chip select control block configured to generate first and second chip select control signals by using the chip select mode signal and the predetermined address signal; and
a RAS control block configured to receive the first and second chip select control signals, the first and second chip select signals, a precharge command signal, and the bank mode signal to generate first and second active signals and first and second precharge signals.
10. The semiconductor memory apparatus of claim 9 , wherein the chip select control block includes:
a first chip select control unit configured to generate the first chip select control signal in response to the chip select mode signal and the predetermined address signal; and
a second chip select control unit configured to generate the second chip select control signal in response to an inverted level of the chip select mode signal and the predetermined address signal.
11. The semiconductor memory apparatus of claim 9 , wherein the RAS control block includes:
a first RAS control unit configured to control precharge and activation of the first bank block; and
a second RAS control unit configured to control precharge and activation of the second bank block.
12. The semiconductor memory apparatus of claim 11 , wherein the first RAS control unit generates the first active signal in response to the first chip select control signal.
13. The semiconductor memory apparatus of claim 12 , wherein the second RAS control unit generates the second active signal in response to the second chip control signal.
14. The semiconductor memory apparatus of claim 11 , wherein the first and second RAS control units generate the first and second precharge signals according to the bank mode signal and the first or second chip select control signal if the precharge command signal is activated.
15. The semiconductor memory apparatus of claim 14 , wherein the first and second RAS control units simultaneously or selectively activate the first and second precharge signals in response to the bank mode signal.