Method for manufacturing semiconductor device preventing loss of junction region
View Patent ↗A method for manufacturing a semiconductor device includes forming an insulation layer having a contact hole on a semiconductor substrate. A metal silicide layer is deposited on a surface of the contact hole and the insulation layer to have a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, with the lower portion of the metal silicide layer having the silicon-rich composition and the upper portion of the metal silicide layer having the metal-rich composition. The metal silicide layer is then annealed so that the compositions of metal and silicon in the metal silicide layer become uniform.
1. A method for manufacturing a semiconductor device, comprising the steps of:
forming an insulation layer having a contact hole on a semiconductor substrate;
depositing a metal silicide layer on a surface of the contact hole and the insulation layer, the metal silicide having a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, wherein a lower portion of the metal silicide layer has the silicon-rich composition and an upper portion of the metal silicide layer has the metal-rich composition; and
annealing the metal silicide layer such that compositions of metal and silicon in the metal silicide layer become uniform.
2. The method according to claim 1 , further comprising the step of:
after forming the insulation layer having the contact hole and before depositing the metal silicide layer, cleaning the resultant semiconductor substrate including a bottom of the contact hole.
3. The method according to claim 1 , wherein the metal silicide layer is deposited through a CVD process.
4. The method according to claim 1 , wherein the metal silicide layer comprises a CoSi x layer.
5. The method according to claim 1 , wherein the metal to silicon composition ratio is in the range of 1:3˜1:10 in the silicon-rich portion of the metal silicide layer.
6. The method according to claim 1 , wherein the metal to silicon composition ratio is in the range of 1:0.1˜1:0.9 in the metal-rich portion of the metal silicide layer.
7. The method according to claim 1 , further comprising the step of:
after depositing the metal silicide layer and before annealing the metal silicide layer, depositing a capping layer on the metal silicide layer.
8. The method according to claim 7 , wherein the step of depositing the capping layer is implemented in situ with respect to the step of depositing the metal silicide layer.
9. The method according to claim 7 , wherein the capping layer comprises a Ti layer or a TiN layer.
10. The method according to claim 1 , wherein annealing is conducted at a temperature in the range of 700˜850 C.
11. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate and a junction region on a semiconductor substrate;
forming an insulation layer on the semiconductor substrate;
etching the insulation layer to define a contact hole exposing the junction region;
depositing a metal silicide layer on a surface of the contact hole and the insulation layer, the metal silicide layer having a concentration gradient that changes from a silicon-rich composition to a metal-rich composition, wherein a lower portion of the metal silicide layer has the silicon-rich composition and an upper portion of the metal silicide layer has the metal-rich composition; and
annealing the metal silicide layer such that compositions of metal and silicon in the metal silicide layer become uniform.
12. The method according to claim 11 , further comprising the step of:
after forming the insulation layer having the contact hole and before depositing the metal silicide layer, cleaning the resultant semiconductor substrate including a bottom of the contact hole.
13. The method according to claim 11 , wherein the metal silicide layer is deposited through a CVD process.
14. The method according to claim 11 , wherein the metal silicide layer comprises a CoSi x layer.
15. The method according to claim 11 , wherein the metal to silicon composition ratio is in the range of 1:3˜1:10 in the silicon-rich portion of the metal silicide layer.
16. The method according to claim 11 , wherein the metal to silicon composition ratio is in the range of 1:0.1˜1:0.9 in the metal-rich portion of the metal silicide layer.
17. The method according to claim 11 , further comprising the step of:
after depositing the metal silicide layer and before annealing the metal silicide layer, depositing a capping payer on the metal silicide layer.
18. The method according to claim 17 , wherein the step of depositing the capping layer is implemented in situ with respect to the step of depositing the metal silicide layer.
19. The method according to claim 17 , wherein the capping layer comprises a Ti layer or a TiN layer.
20. The method according to claim 11 , wherein annealing is conducted at a temperature in the range of 700˜850° C.