Architecturally independent noise sensitivity analysis of integrated circuits having a memory storage device and a noise sensitivity analyzer
View Patent ↗Method of analyzing noise sensitivity of integrated circuits having at least one memory storage device and a noise sensitivity analyzer. In one embodiment, the noise sensitivity analyzer includes a circuit reservoir, a circuit parser and a circuit evaluator. The circuit reservoir is configured to receive and store a model of a circuit having at least one memory storage device to be analyzed. The circuit parser is configured to identify nodes of the model. The circuit evaluator is configured to apply a large test current to each of the nodes for multiple circuit states of the at least one memory storage device and determine which of the nodes are sensitive nodes.
1. A noise sensitivity analyzer, comprising:
a circuit reservoir configured to receive and store a model of a circuit having at least one memory storage device to be analyzed;
a circuit parser configured to identify nodes of said model; and
a circuit evaluator configured to apply a test current to each of said nodes for multiple circuit states of said at least one memory storage device and determine which of said nodes are sensitive nodes, wherein said multiple circuit states include each possible logic state of said at least one memory storage device.
2. The noise sensitivity analyzer as recited in claim 1 , wherein said circuit evaluator is configured to apply said test current to only one of said nodes at a time.
3. The noise sensitivity analyzer as recited in claim 1 , wherein said circuit evaluator is further configured to apply at least one other test current to said nodes identified as sensitive nodes until determining a critical charge of said nodes identified as sensitive nodes.
4. The noise sensitivity analyzer as recited in claim 1 , wherein said circuit evaluator is further configured to apply at least one other test current to all of said nodes.
5. The noise sensitivity analyzer as recited in claim 1 , wherein said at least one storage memory device is a cell storage element and said circuit evaluator is configured to apply said test current to each of said nodes for said multiple circuit states wherein said multiple circuit states further include both clock states for said cell storage element.
6. The noise sensitivity analyzer as recited in claim 1 , wherein said circuit evaluator is configured to apply said test current to multiple of said nodes simultaneously.
7. The noise sensitivity analyzer as recited in claim 1 , wherein said circuit evaluator is configured to apply said test current employing an electrical current simulator.
8. A method of analyzing a circuit for noise sensitivity, comprising:
receiving, by a processor, a model of a circuit having at least one memory storage device to be analyzed;
identifying nodes of said model;
applying a test current to each of said nodes for multiple circuit states of said at least one memory storage device, wherein said multiple circuit states include each possible logic state of said at least one memory storage device; and
determining which of said nodes are sensitive nodes.
9. The method as recited in claim 8 , wherein said applying said test current includes applying said large test current to only one of said nodes at a time.
10. The method as recited in claim 8 , further comprising applying at least one other test current to said nodes identified as sensitive nodes until determining a critical charge of said nodes identified as sensitive nodes.
11. The method as recited in claim 8 , further comprising applying at least one other test current to all of said nodes.
12. The method as recited in claim 8 , wherein said at least one storage memory device is a cell storage element and said applying includes applying a test current to each of said nodes for said multiple circuit states wherein said multiple circuit states further include both clock states of said cell storage element.
13. The method as recited in claim 8 further comprising simultaneously applying said test current to multiple of said nodes.
14. The method as recited in claim 8 , wherein said value of said test current is based on the fabrication technology of said circuit.
15. A method of determining a critical charge of a node of a memory storage device, comprising the steps of:
(a) receiving, by a processor, a model of a circuit having at least one memory storage device to be analyzed;
(b) identifying nodes of said model;
(c) applying a test current to one of said nodes for multiple circuit states of said at least one memory storage device, wherein said multiple circuit states include each possible logic state of said at least one memory storage device;
(d) determining if said one node is a sensitive node for each of said multiple circuit states; and
(e) applying additional test currents to said one node if said one node is a sensitive node until a critical charge of said one node is determined.
16. The method as recited in claim 15 , wherein step (e) includes refining values of said test currents until a logic state of said memory storage device is undisturbed.
17. The method as recited in claim 15 , wherein said large test current is based on a fabrication technology of said circuit.
18. The method as recited in claim 15 , wherein steps (c) to (e) are repeated for each of said nodes.