Forming robust solder interconnect structures by reducing effects of seed layer underetching

1. A method for forming an interconnect structure for a semiconductor device, the method comprising:

defining a via in a passivation layer so as expose a top metal layer in the semiconductor device;

forming a seed layer over said passivation layer, sidewalls of said via, and said top metal layer;

forming a barrier layer over an exposed portion of said seed layer, said exposed portion defined by a first patterned opening of a first diameter; and

forming a solder material over said barrier layer using a second patterned opening of a second diameter;

wherein said second patterned opening is configured such that said second diameter is larger than said first diameter.

2. The method of claim 1 , further comprising removing exposed portions of said seed layer so as to define a ball limiting metallurgy (BLM), wherein remaining portions of said seed layer do not undercut said barrier layer.

3. The method of claim 1 , wherein:

said seed layer comprises a titanium-tungsten/chrome-copper/copper (TiW/CrCu/Cu) layer; and

said barrier layer comprises a nickel/copper layer.

4. The method of claim 3 , wherein copper and chrome copper portions of seed layer are removed by electroetching.

5. The method of claim 4 , wherein said second diameter exceeds said first diameter by about 20 to about 25 microns.