Granted Patent B2

US 8,156,352 · App. 12/360,760 · Granted Apr 10, 2012

Abstract

Claims (37)

1. A peripheral bus power controller comprising:

a first terminal of the peripheral bus power controller;

a second terminal coupled to receive a power enable input signal from a host controller;

a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller;

an enable circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal, wherein the enable circuit includes a first buffer coupled to receive the power enable input signal and a resistor coupled between an output of the first buffer and first terminal; and

a second buffer configured to provide the over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.

2. The power controller as recited in claim 1 , wherein the power controller is implemented in an integrated circuit package having a plurality of pins, wherein the first terminal is coupled to one of the plurality of pins.

3. The power controller as recited in claim 1 ,

wherein the enable circuit further includes an inverter having an inverter input coupled to the second terminal, and a third buffer, wherein the third buffer has a signal input coupled to an electrical ground, an enable input coupled to an output of the inverter, and an output coupled to the first terminal.

4. The power controller as recited in claim 1 , further comprising a filter coupled to an output of the second buffer.

5. The power controller as recited in claim 1 ,

wherein the power enable output signal is driven at a first logic level onto the first terminal, and wherein detecting an over-current condition includes detecting a second logic level on the first terminal.

6. The power controller as recited in claim 5 ,

wherein the first logic level is a logic high level, and wherein the second logic level is a logic low level.

7. A computer system comprising:

a peripheral bus host controller; and

at least one peripheral port coupled to a peripheral bus and the host controller, wherein the at least one peripheral port includes a peripheral bus power controller comprising:

a first terminal of the peripheral bus power controller;

a second terminal coupled to receive a power enable input signal from the host controller;

a third terminal coupled to provide an over-current output signal indicative of an over-current condition to the host controller;

a first circuit configured to assert a power enable output signal on the first terminal responsive to receiving the power enable input signal, wherein the first circuit includes a first buffer coupled to receive the power enable input signal from the host controller, a resistor coupled between an output of the first buffer and the first terminal, an inverter having an inverter input coupled to the second terminal, and a second buffer, wherein the second buffer has a signal input coupled to an electrical ground, an enable input coupled to an output of the inverter, and an output coupled to the first terminal; and

a second circuit configured to provide an over-current output signal to the host controller responsive to the power controller detecting the over-current condition on the first terminal.

8. The computer system as recited in claim 7 ,

wherein the peripheral bus power controller is implemented in an integrated circuit package having a plurality of pins, and wherein the first terminal is coupled to one of the plurality of pins.

9. The computer system as recited in claim 7 ,

wherein the peripheral port further includes a power switch coupled to the first terminal of the peripheral bus power controller, wherein the power switch is configured to provide power to a peripheral device coupled to the peripheral bus responsive to receiving the power enable output signal from the peripheral bus power controller.

10. The computer system as recited in claim 8 ,

wherein the peripheral port further includes a resettable fuse coupled between a first voltage node and a second voltage node, and a diode having an anode coupled to the first terminal and a cathode coupled to the second voltage node.

11. The computer system as recited in claim 10 , wherein the resettable fuse is configured to open responsive to an over current condition.

12. The computer system as recited in claim 7 , further comprising a peripheral device coupled to the peripheral bus, wherein the peripheral device is coupled to receive power through the second voltage node.

13. The computer system as recited in claim 8 , wherein the peripheral bus includes a true data signal path and a complementary signal data path.

14. The computer system as recited in claim 7 , wherein the second circuit comprises a third buffer having an input coupled to the first terminal.

15. The computer system as recited in claim 14 , wherein the peripheral bus power controller further includes a filter coupled between the host controller and an output of the third buffer.

16. The computer system as recited in claim 7 ,

wherein the power enable output signal is driven at a first logic level onto the first terminal, and wherein detecting an over-current condition includes detecting a second logic level on the first terminal.

17. The computer system as recited in claim 16 , wherein the first logic level is a logic high level, and wherein the second logic level is a logic low level.

18. The computer system as recited in claim 7 , wherein the peripheral bus is a Universal Serial Bus.

Assignments (10)