IP Library Granted Patent US 8,071,427
Granted Patent B2
US 8,071,427 · App. 12/362,142 · Granted Dec 6, 2011

Method for manufacturing a semiconductor component and structure therefor

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Quick Facts
Patent No.
US 8,071,427
App. No.
12/362,142
Granted
Dec 6, 2011
Kind
B2
Abstract

A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.

Claims (22)

1. A method for manufacturing a semiconductor component, comprising:

providing one or more electrical interconnect structures partially embedded in a mold compound, the one or more electrical interconnect structures having first and second major surfaces and a plurality of edges coupling the first major surface to the second major surface;

exposing a portion of a first edge of the plurality of edges of at least one of the one or more electrical interconnect structures;

forming a first material over a sub-portion of the exposed portion of the first edge; providing a leadframe having a tie bar with first and second leadframe leads extending from opposing sides of the tie bar; forming a wirebond from the first leadframe lead to the second leadframe lead, and separating the mold compound into at least two portions, wherein the separating includes cutting and separating the wirebond.

2. The method of claim 1 , wherein forming the first material over the sub-portion of the exposed portion of the first edge comprises plating the first material onto the exposed portion of the first edge of the at least one electrical interconnect structure.

3. The method of claim 1 , wherein exposing the portion of the first edge of the plurality of edges of the at least one of the one or more electrical interconnect structures comprises sawing the at least one electrical interconnect structure.

4. The method of claim 1 , wherein separating the mold compound into at least two portions includes sawing through the mold compound.

5. The method of claim 1 , wherein exposing the portion of the first edge of the plurality of edges of the at least one of the one or more electrical interconnect structures comprises stamping the one or more electrical interconnect structures.

6. The method of claim 1 , wherein exposing the portion of the first edge of the plurality of edges of the at least one of the one or more electrical interconnect structures comprises etching the one or more electrical interconnect structures.

7. The method of claim 1 , wherein forming the first material over a sub-portion of the exposed portion of the first edge includes forming an electrically conductive material over the exposed portion.

8. The method of claim 7 , wherein forming the first material over a sub-portion of the exposed portion of the first edge includes forming an anti-oxidizing coating over the exposed portion.

9. The method of claim 1 , wherein forming the first material over the sub-portion of the exposed portion of the first edge includes barrel plating the first material over the sub-portion of the exposed portion of the first edge.

10. The method of claim 1 , wherein providing the one or more electrical interconnect structures embedded in the mold compound includes:

providing a leadframe having a tie bar with first and second leadframe leads extending from opposing sides of the tie bar;

further including forming a dimple in at least a portion of the tie bar.

11. The method of claim 10 , wherein forming the dimple comprises stamping the portion of the tie bar.

12. A method for manufacturing a semiconductor component, comprising:

providing a leadframe partially embedded in a molding compound having first and second major surfaces and a plurality of leadframe leads, wherein each of the plurality of leadframe leads has an edge coupling the first major surface to the second major surface;

exposing a portion of a first edge of at least one leadframe lead of the plurality of leadframe leads;

forming a first layer of conductive material on at least a sub-portion of the exposed portion of the first edge of the at least one leadframe lead of the plurality of leadframe leads, wherein the leadframe includes a tie bar with first and second leadframe leads extending from opposing sides of the tie bar, and further includes forming a wirebond from the first leadframe lead to the second leadframe lead or forming a dimple in the tie bar, and separating the mold compound into at least two portions, wherein the separating includes cutting and separating the wirebond.

13. The method of claim 12 , further including forming a second layer of electrically conductive material on the exposed portion of the first edge of the at least one leadframe lead followed by exposing the portion of the at least one leadframe lead.

14. The method of claim 13 , wherein exposing the portion of the first edge of the at least one leadframe lead of the plurality of leadframe leads includes using a method selected from the group of methods comprising sawing the leadframe, etching the leadframe, stamping the leadframe, and nicking the leadframe.

Assignments (2)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →