USB port overvoltage protection
View Patent ↗A system and method for efficient input/output (I/O) port overvoltage protection of a high-speed port. An interfacing system for connecting peripheral devices to a computing system comprises ports for conveying serial communications bi-directional signals and an overvoltage protection circuit. The protection circuit prevents an overvoltage condition on one port in response to an overvoltage event on a corresponding second port. In one embodiment, the interfacing system connects USB peripheral devices to an automotive infotainment system comprising an automotive battery potiential greater than a USB power supply. In addition, the overvoltage protection circuit is able to transmit signals between the two ports without signal attenuation defined by an industry standard specification such as Universal Serial Bus (USB) Implementers Forum (IF) eye pattern diagram test. The overvoltage protection circuit is configured to have a small footprint, and, therefore, does not utilize a power reference and comparator circuit.
1. An overvoltage protection circuit comprising:
a first node configured to send and receive signals;
a second node configured to send and receive signals, wherein the first node and the second node are connected by a transmission line and a series connection impedance, wherein the transmission line has an impedance and wherein the series connection impedance has an impedance that is less than five percent of the impedance of the transmission line and wherein the transmission line and series connection impedance are connected in parallel;
a third node coupled to a power supply, wherein the power supply is connected to a switching circuit of the protection circuit by a series resistor that has an impedance at least three times the impedance of the transmission line wherein the impedance of the series resistor prevents the power supply from shorting signals on the transmission line; and
the switching circuit configured to:
connect the first node and the second node in response to detecting a signal on either the first node or the second node that reaches a first threshold voltage;
transmit the signal through the impedance of the transmission line; and
disconnect the first node and the second node from one another, responsive to detecting the signal reaches a second threshold voltage above a power supply reference.
2. The overvoltage protection circuit as recited in claim 1 , wherein the switching circuitry comprises only one nmos transistor having a drain terminal coupled to the first node and a source terminal coupled to the second node, wherein each of the first node and the second node transmits bidirectional signals.
3. The overvoltage protection circuit as recited in claim 2 , wherein a combination of a frequency of the signal and an equivalent parasitic gate capacitance of the nmos transistor produces a gate capacitive reactance less than twenty percent of the transmission line impedance on the first node.
4. The overvoltage protection circuit as recited in claim 3 , prevents electrical shorting of the transmitted signal to the third node through the gate capacitive reactance when the nmos transistor is in an on state.
5. The overvoltage protection circuit as recited in claim 4 , wherein a series connection capacitance to ground is less than a parasitic capacitance.
6. The overvoltage protection circuit as recited in claim 5 , wherein the switching circuitry is further configured to suppress signal ringing during said disconnect via a series resistor-capacitor chain between the first node and the second node.
7. The overvoltage protection circuit as recited in claim 5 , wherein said signal is a Universal Serial Bus (USB) high-speed mode signal.
8. The overvoltage protection circuit as recited in claim 5 , wherein said signal is a serial bus communication signal.
9. An interfacing system for providing overvoltage protection, the interfacing system comprising:
one or more input ports each configured to send and receive signals and each said input port connected to a corresponding output port by a transmission line and a series connection impedance, wherein the series connection impedance has an impedance that is less than five percent of the impedance of the transmission line and wherein the transmission line and the series connection impedance are connected in parallel;
a power supply;
an overvoltage protection circuit for each input port comprising a first node coupled to a corresponding input port, a second node coupled to a corresponding output port, and a third node coupled to the power supply, wherein the power supply is connected to the other components of the system via a series resistor that has an impedance at least three times the impedance of the transmission line; and
wherein the overvoltage protection circuit is configured to:
connect the first node and the second node in response to detecting a signal on either the first node or the second node that reaches a first threshold voltage;
transmit the signal through the impedance of the transmission line; and
disconnect the first node and the second node from one another, responsive to detecting the signal reaches a second threshold voltage above a power supply reference.
10. The interfacing system as recited in claim 9 , wherein the overvoltage protection circuit comprises only one nmos transistor having a drain terminal coupled to the first node and a source terminal coupled to the second node, wherein each of the first node and the second node transmits bidirectional signals.
11. The interfacing system as recited in claim 9 , wherein a combination of a frequency of the signal and an equivalent parasitic gate capacitance of the nmos transistor produces a gate capacitive reactance less than twenty percent of the transmission line impedance on the first node.
12. The interfacing system as recited in claim 11 , wherein the series resistor prevents electrical shorting of the transmitted signal to the third node through the gate capacitive reactance when the nmos transistor is in an on state.
13. The interfacing system as recited in claim 12 , wherein a series connection capacitance to ground is less than a parasitic capacitance.
14. The interfacing system as recited in claim 13 , wherein the overvoltage protection circuit is further configured to suppress signal ringing during said disconnect via a series resistor-capacitor chain between the first node and the second node.
15. The interfacing system as recited in claim 13 , wherein said signal is a Universal Serial Bus (USB) high-speed mode signal.
16. The interfacing system as recited in claim 13 , wherein said signal is a serial bus communication signal.
17. An overvoltage protection method in a data bus interface, the method comprising:
receiving a signal on a first node;
connecting the first node and a second node by a transistor coupled to a transmission line, responsive to detecting a signal on either the first node or the second node that reaches a first threshold voltage, wherein the first node and a second node are additionally coupled by a series connection impedance that is less than five percent of a transmission line impedance on the first node;
transmitting the signal through the series connection impedance; and
disconnecting the transmission line between the first node and the second node using the transistor, responsive to detecting the signal reaches a second threshold voltage above the power supply, wherein the power supply is connected to the transistor via a series resistor that has an impedance at least three times the impedance of the transmission line.
18. The method as recited in claim 17 , wherein said transmitting the signal utilizes only one nmos transistor having a drain terminal coupled to the first node and a source terminal coupled to the second node, wherein each of the first node and the second node transmits bidirectional signals.
19. The method as recited in claim 18 , wherein a combination of a frequency of the signal and an equivalent parasitic gate capacitance of the nmos transistor produces a gate capacitive reactance less than twenty percent of the transmission line impedance on the first node.
20. The method as recited in claim 19 , wherein the series resistor prevents electrical shorting of the transmitted signal to the third node through the gate capacitive reactance when the nmos transistor is in an on state.