Fractured erase system and method
View Patent ↗Efficient and convenient storage systems and methods are presented. In one embodiment, a fractured erase process is performed in which a pre-program process, erase process and soft program process are initiated independently. Memory cells can be pre-programmed and conditioned independent of an erase command. The initiation of the independent pre-programming is partitioned from an erase command which is partitioned from initiation of a soft-programming command. A cell is erased wherein the erasing includes erase operations that are partitioned from the pre-preprogramming process. In one embodiment, the independent pre-program process is run in the background.
1. A memory alteration process comprising:
initiating an independent pre-programming process on a cell previously used to store data, without necessity of an erase indication;
receiving an indication to write data to a cell that has been independently pre-programmed;
initiating an independent erase operation;
erasing the cell; and
performing an independent soft programming operation on the cell.
2. A memory alteration process of claim 1 the independent pre-program process is run in the background and the initiating the independent pre-programming process is begun before an erase indication.
3. A memory alteration process of claim 1 further comprising issuing a pre-program command to condition portions of the memory.
4. A memory alteration process of claim 3 wherein the pre-program command is associated with conditioning of a page in a target block.
5. A memory alteration process of claim 1 wherein said independent erase further comprising issuing an erase command that initiates a programming of target storage bits to a static state.
6. A memory alteration process of claim 1 wherein the independent pre-programming drives a memory cell bit to a logical value opposite of a static state.
7. A memory alteration process of claim 1 further comprising:
interrupting with an operation other than an erase; and
restarting the erasing.
8. A memory alteration process of claim 1 further comprising interrupting with a program operation; and
restarting the erasing.
9. A memory system comprising:
a memory for storing information; and
a memory control component for controlling communication of the information between a host and the memory, including directing a fractured erase process in which pre-programming is performed on portions of said memory previously used to store information without necessity of an erase indication.
10. A memory system of claim 9 wherein the memory control component is integrated in a host for processing the information.
11. A memory system of claim 9 wherein the memory control component is external to a host for processing the information.
12. A memory system of claim 11 wherein the memory is partitioned in to multiple blocks with each block containing a plurality of pages and an independent pre-programming process programs the bits to a predetermined logical state in page by page manner within a target erase block.
13. A memory system of claim 9 wherein the independent pre-programming includes driving a bit to a logical value opposite of a static state independent of an erase indication.
14. A memory system of claim 9 wherein the memory control component interrupts an erase sequence to perform a program operation and returns to the erase operation at an appropriate time.