Power management control and controlling memory refresh operations
A memory device providing signals indicating when refresh operations are complete. The signals from a number of memory devices can be combined, such as by Oring, to provide a refresh complete signal to a power management controller. Dynamic factors can affect the refresh operation and the memory may be refreshed without restoring the entire system to a high power state. The time required to perform a refresh operation can be determined dynamically, allowing the system to be returned to a low power state as soon as refresh is complete. Ambient temperatures can be monitored to dynamically determine when to perform a refresh operation.
1. A memory refresh circuit comprising:
a control circuit for monitoring memory devices and for indicating when a refresh operation on the memory devices is complete, based on the monitoring of the memory device; and
a power management circuit coupled to memory devices for controlling power provided to the memory devices.
2. The circuit of 1 , wherein the control conducts the refresh operation on the memory devices.
3. The circuit of claim 1 , wherein the memory circuit can perform a burst self-refresh operation.
4. The circuit of claim 3 , wherein the memory refresh circuit performs the burst self-refresh operation if the control circuit senses certain conditions.
5. The circuit of claim 1 , wherein the memory refresh circuit includes a refresh counter.
6. The circuit of claim 5 , wherein the control circuit controls the refresh counter.
7. The circuit of claim 5 , wherein the refresh counter provides a signal indicating when said refresh operation is complete.
8. A memory device comprising:
a memory array; and
a refresh circuit for monitoring the memory array for indicating when a refresh operation on the memory array is complete, based on the monitoring of the memory device; and
a power management circuit coupled to a memory device comprising the memory array for controlling power provided to the memory device.
9. The device of claim 8 , wherein the refresh circuit includes a control circuit.
10. The device of claim 9 , wherein the refresh circuit can perform a burst self-refresh operation.
11. The device of claim 10 , wherein the refresh circuit performs the burst self-refresh operation if the control circuit senses certain conditions.
12. The device of claim 9 , wherein the refresh circuit includes a refresh counter.
13. The device of claim 12 , wherein the control circuit controls the refresh counter.
14. The device of claim 12 , wherein the refresh counter provides a signal indicating when said refresh operation is complete.
15. The device of claim 8 , wherein the refresh circuit controls a memory refresh operation on the memory array.
16. A memory system, comprising:
a plurality of memory devices, each comprising:
a memory array; and
a refresh circuit for monitoring the memory array and for providing a refresh complete signal when a refresh operation on the memory array is complete, based on the monitoring of the memory device; and
a power management circuit coupled to memory devices for controlling power provided to the memory devices.
17. The memory system of claim 16 ,
further comprising a combining circuit for combining the refresh complete signals from the memory devices.
18. The memory system of claim 16 , wherein the refresh circuit includes a fresh counter.
19. The memory system of claim 16 , further comprising a temperature integration circuit for incorporating temperature into determining when a refresh operation should be performed.
20. The memory of claim 19 , wherein the temperature integration circuit is adapted to receive signals from a temperature sensor for measuring temperature.
21. The memory system of claim 20 , wherein the temperature sensor is located outside the memory system.
22. The memory system of claim 20 , wherein the temperature sensor is located inside the memory system.