Granted Patent B2

US 8,154,270 · App. 12/371,375 · Granted Apr 10, 2012

Abstract

Claims (66)

1. An input protection circuit comprising:

a first circuit configured to compare an input signal to a reference signal, and generate a first control signal indicative of whether the value of the input signal is greater than or equal to the value of the reference signal, or less than the value of the reference signal;

a second circuit configured to receive the first control signal, and generate a second control signal according to the first control signal, wherein the second control signal is set to a first specified value for a first value of the first control signal, and wherein a value of the second control signal tracks the value of the input signal for a second value of the first control signal; and

a third circuit configured to generate an output signal according to the first control signal and the second control signal, wherein a value of the output signal tracks the value of the input signal for the first value of the first control signal and the first specified value of the second control signal, and wherein the value of the output signal is set to a second specified value less than the value of the input signal for the second value of the first control signal.

2. The input protection circuit of claim 1 , wherein the first value of the first control signal is indicative of the value of the input signal being less than the value of the reference signal, and wherein the second value of the first control signal is indicative of the input signal being greater than or equal to the value of the reference signal.

3. The input protection circuit of claim 1 , wherein the second circuit is a level shifter circuit, having a first branch powered by a first supply voltage and a second branch powered by an attenuated version of the input signal.

4. The input protection circuit of claim 1 , wherein the third circuit is a multiplexer configured to:

receive the input signal as a first input;

receive a second signal having the second specified value as a second input; and

switch between the first input and the second input to be the output signal, according to the value of the first control signal and the value of the second control signal.

5. The input protection circuit of claim 1 , wherein the second specified value, and the value of the reference signal are each equal to the value of a power supply voltage used to power the input protection circuit.

6. A protection circuit comprising:

a first component configured to:

receive an input voltage and a reference voltage;

assert a first control signal when the input voltage is greater than or equal to the reference voltage; and

deassert the first control signal when the input voltage is less than the reference voltage;

a second component configured to:

deassert a second control signal when the first control signal is deasserted;

set the second control signal to track the input voltage when the first control signal is asserted; and

a third component configured to:

set an output voltage to a specified voltage less than the input voltage when the first control signal is asserted; and

set the output voltage to track the input voltage when the first control signal and the second control signal are both deasserted.

7. The protection circuit of claim 6 , wherein the first component, second component, and third component comprise CMOS devices, wherein the first component, and at least a portion of the second component are powered by a specified supply voltage.

8. The protection circuit of claim 7 , wherein the second component is a level shifter comprising a first branch powered by the specified supply voltage, and a second branch powered by a second supply voltage based on the input voltage; wherein the second branch of the level shifter comprises PMOS devices having a floating well to keep the respective well of each of the PMOS devices at a highest possible voltage level.

9. The protection circuit of claim 8 , wherein the level shifter further comprises a bias circuit coupled between the specified supply voltage and reference ground to set a control voltage level at a control terminal of a transistor device in an output stage of the level shifter.

10. The protection circuit of claim 8 , further comprising a resistor coupled between the input voltage and the level shifter to provide protection against latch-up.

11. The protection circuit of claim 9 , wherein a total threshold voltage for the bias circuit is greater than the specified supply voltage.

12. The protection circuit of claim 9 , wherein the bias circuit comprises diode-connected transistors having their channels coupled in series.

13. The protection circuit of claim 6 , wherein the third component is an analog multiplexer comprising:

a pair of transmission gates coupled in series, controlled by the second control signal and the first control signal, and having one end coupled to the input voltage and the other end coupled to an output node configured to provide the output voltage; and

a transistor having a control terminal controlled by the first control signal, and having a first channel terminal configured to receive the specified voltage and the other channel terminal coupled to the output node;

wherein the pair of transmission gates are configured to relay the input voltage to the output node when the first control signal and the second control signal are both deasserted; and

wherein the transistor device is configured to relay the specified voltage to the output node when the first control signal is asserted.

14. A method for protecting a system from high voltage, the method comprising:

comparing an input voltage to a reference voltage;

generating a first control signal in response to said comparing, wherein the first control signal is indicative of whether the input voltage is greater than or equal to the reference voltage, or less than the reference voltage;

setting a second control signal:

to a first specified voltage in response to the first control signal indicating that the input voltage is less than the reference voltage; and

to the input voltage in response to the first control signal indicating that the input voltage is greater than or equal to the reference voltage; and

setting an output:

to a second specified voltage less than the input voltage in response to the first control signal indicating that the input voltage is greater than or equal to the reference voltage; and

to the input voltage in response to:

the first control signal indicating that the input voltage is less than the reference voltage; and

said setting the second control signal to the first specified voltage.

15. The method of claim 14 , wherein the reference voltage and the second specified voltage are equal to a supply voltage configured to provide power to the system.

16. The method of claim 14 , wherein said generating the first control signal comprises asserting the first control signal when the input voltage is greater than or equal to the reference voltage, and deasserting the first control signal when the input voltage is less than the reference voltage.

17. The method of claim 14 , wherein said setting the output to the input voltage comprises:

controlling a pair of transmission gates with the first control signal and the second control signal; and

the transmission gates relaying the input voltage from an input of the transmission gates to the output.

18. The method of claim 14 , wherein said setting the output to the second specified voltage comprises controlling a transistor device with the first control signal to relay the second specified voltage from one of its channel terminals to the output.

19. An integrated circuit comprising:

a function block;

at least one input pin configured to receive an input signal intended for at least one specific destination within the function block, the input signal having a voltage value; and

a protection circuit coupled between the at least one input pin and the function block, wherein the protection circuit is configured to:

allow the input signal to propagate to the at least one specific destination within the function block when the voltage value of the input signal does not exceed the value of a specified reference voltage; and

provide a replacement signal to propagate to the at least one specific destination within the function block instead of the input signal when the voltage value of the input signal exceeds the value of the specified reference voltage, wherein the voltage value of the replacement signal is no greater than the value of a supply voltage configured to power the integrated circuit, and wherein the voltage value of the replacement signal corresponds to the logic level represented by the voltage value of the input signal.

20. The integrated circuit of claim 19 , wherein the voltage value of the replacement signal is the same as the value of the supply voltage.

21. The integrated circuit of claim 20 , wherein the value of the specified reference voltage is the same as the value of the supply voltage.

22. A method for protecting a system against high voltage, the method comprising:

receiving an input signal intended for at least one specific destination within the system, the input signal having a voltage value;

intercepting the input signal before it reaches the at least one specific destination within the system;

allowing the input signal to propagate to the at least one specific destination within the system when the voltage value of the input signal does not exceed the value of a specified reference voltage; and

generating a replacement signal to replace the input signal when the voltage value of the input signal exceeds the value of the specified reference voltage, wherein the voltage value of the replacement signal is no greater than the value of a supply voltage configured to provide power to the system, and wherein the voltage value of the replacement signal corresponds to the logic level represented by the voltage value of the input signal.

23. The method of claim 22 , further comprising propagating the replacement signal to the at least one specific destination within the system.

24. The method of claim 22 , wherein the system is an integrated circuit, wherein said receiving the input signal is at a pin of the integrated circuit.

25. The method of claim 24 , wherein the integrated circuit is fabricated using a fabrication process yielding CMOS devices.

Assignments (10)