Semiconductor integrated circuit including plurality of bonding pads
View Patent ↗A semiconductor integrated circuit includes a plurality of bonding pads formed along an edge of a semiconductor substrate; a plurality of I/O cells arranged along the edge under the plurality of bonding pads; an upper layer wire mesh including a plurality of upper layer wirings; and a core region formed on the semiconductor substrate. In the semiconductor integrated circuit, the core region has an area larger than an area occupied by the upper layer wire mesh in a plane parallel to a surface of the semiconductor substrate.
1. A semiconductor integrated circuit comprising:
a plurality of bonding pads provided along an edge of a semiconductor substrate;
a plurality of I/O cells arranged along the edge under the plurality of bonding pads;
an upper layer wire mesh comprising a plurality of upper layer wirings;
a core region formed on the semiconductor substrate; and
a lower layer wire mesh formed between the semiconductor substrate and the upper layer wire mesh,
wherein the core region has an area larger than an area occupied by the upper layer wire mesh in a plane parallel to a surface of the semiconductor substrate;
wherein each of the plurality of bonding pads has a thickness equal to a thickness of the upper layer wire mesh including wiring layers;
wherein at least one wiring layer included in the lower layer wire mesh is formed so as to correspond to the core region.
2. The semiconductor integrated circuit according to claim 1 , wherein:
the upper layer wire mesh comprises an upper layer annular power supply wiring; and
the lower layer wire mesh comprises a lower layer annular power supply wiring formed under the plurality of bonding pads.
3. The semiconductor integrated circuit according to claim 2 , wherein:
the plurality of bonding pads comprise:
a power supply pad; and
a signal supply pad for supplying a signal to at least one of the plurality of I/O cells; and
the power supply pad is connected to the lower layer annular power supply wiring through a via contact, and to the upper layer annular power supply wiring through a wiring pattern in the upper layer wire mesh.
4. The semiconductor integrated circuit according to claim 3 , wherein the plurality of bonding pads comprise:
a first pad group arranged along the edge of the semiconductor substrate on which the plurality of I/O cells are formed, the first pad group comprising the power supply pad and the signal supply pad; and
a second pad group arranged in a row different from a row in which the first pad group is arranged, the second pad group being formed between the first pad group and the edge.
5. The semiconductor integrated circuit according to claim 4 , wherein the first pad group is arranged so as to cover at least a part of an I/O region and at least a part of the lower layer wire mesh.
6. A semiconductor integrated circuit, comprising:
an I/O region formed on a semiconductor substrate and comprising a plurality of I/O cells arranged thereon;
a core region formed on the semiconductor substrate and surrounded by the I/O region;
a plurality of bonding pads arranged along a peripheral edge of an IC chip;
an upper layer wire mesh formed in the same layer as the plurality of bonding pads and arranged in a region surrounded by the plurality of bonding pads; and
a lower layer wire mesh arranged between the upper layer wire mesh and the semiconductor substrate,
wherein the lower layer wire mesh comprises:
a first lower layer wire mesh formed between the upper layer wire mesh and the core region; and
a second lower layer wire mesh formed between the plurality of bonding pads and the core region.
7. The semiconductor integrated circuit according to claim 6 , wherein:
the upper layer wire mesh comprises an upper layer annular power supply wiring;
the second lower layer wire mesh comprises a lower layer annular power supply wiring formed under the plurality of bonding pads; and
the core region comprises a logic cell operating according to electric power supplied through the upper layer annular power supply wiring and the lower layer annular power supply wiring.
8. The semiconductor integrated circuit according to claim 7 , wherein:
the plurality of bonding pads comprise:
a power supply pad; and
a signal supply pad for supplying a signal to the plurality of I/O cells; and
the power supply pad is connected to the lower layer annular power supply wiring through a via contact, and to the upper layer annular power supply wiring through a wiring pattern.
9. A semiconductor integrated circuit, comprising:
an I/O region comprising an I/O cell arranged therein;
a core region comprising a logic cell arranged therein; and
an expansion core region formed between the I/O region and the core region, and comprising another logic cell arranged therein, wherein:
the I/O region comprises a first bonding pad formed on the I/O cell, for supplying a signal to the I/O cell;
the core region comprises:
an upper layer wire mesh; and
a lower layer wire mesh formed under the upper layer wire mesh; and the expansion core region comprises:
a second bonding pad formed in the same layer as the upper layer wire mesh;
an expansion lower layer wire mesh located under the second bonding pad, and connected to the lower layer wire mesh in the same layer as the lower layer wire mesh; and
an expansion logic cell arranged in an expansion logic cell region formed under the expansion lower layer wire mesh.
10. The semiconductor integrated circuit according to claim 9 , wherein:
the first bonding pad and the second bonding pad comprise:
a signal supply pad for supplying a signal to the I/O cell; and
a power supply pad; and
the power supply pad is connected to an upper layer annular power supply wiring provided in the upper layer wire mesh through a wiring pattern, and to a lower layer annular power supply wiring provided in the lower layer wire mesh formed under the second bonding pad through a via contact.