IP Library Granted Patent US 7,893,670
Granted Patent B2
US 7,893,670 · App. 12/389,581 · Granted Feb 22, 2011

Frequency compensation scheme for stabilizing the LDO using external NPN in HV domain

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Quick Facts
Patent No.
US 7,893,670
App. No.
12/389,581
Granted
Feb 22, 2011
Kind
B2
Abstract

A voltage regulator may comprise a regulator output configured to provide a regulated voltage, which may be controlled by an error amplifier based on the regulated voltage and a reference voltage. The error amplifier may control a source-follower stage to mirror a multiple of the current flowing in the source-follower stage into an internal pass device. A voltage developed by the mirror current may control an external pass device configured to deliver the load current into the regulator output. A first resistor may be configured to decouple a load capacitor coupled between the regulator output and reference ground, when the load current is below a specified value. A second resistor may be configured to create a bias current in the internal pass device even when the external pass device is close to cut-off region. A third resistor may be configured to counter the effects of negative impedance at the control terminal of the external pass device caused by the current-gain of the external pass device. A compensation capacitor and resistor may be coupled in series between the output of the error amplifier and the output of the voltage regulator to provide frequency compensation for the Miller-Effect.

Claims (79)

1. A voltage regulator comprising:

a first output node configured to provide a regulated output voltage;

a second output node configured to couple to a control terminal of an external pass device that has one end of its channel coupled to the first output node to provide a load current for high-voltage applications;

an internal pass device having a first end of its channel coupled to a supply voltage and a second end of its channel coupled to the second output node to control the external pass device;

an error amplifier having a first input configured to receive a reference signal and a second input coupled in a feedback loop with the first output node, and further having an output configured to control a current branch that establishes current flowing in the internal pass device, to control the regulated output voltage; and

a first resistor having a first end coupled to the first output node and a second end coupled to the second output node to create a bias current in the internal pass device when the external pass device is not providing the load current.

2. The voltage regulator of claim 1 , further comprising:

a load capacitor coupled between the first output node and reference ground; and

a second resistor having one end coupled to the first output node and a second end coupled to the first end of the first resistor, to decouple the load capacitor from the feedback loop when the load current has a magnitude lower than a specified value.

3. The voltage regulator of claim 1 , further comprising a second resistor having a first end coupled to the second end of the channel of the internal pass device, and a second end coupled to the second output node to counter effects of negative impedance caused by a current-gain of the external pass device at the control terminal of the external pass device.

4. The voltage regulator of claim 1 , further comprising a compensation capacitor having a first end coupled to the output of the error amplifier and a second end coupled to the second output node, to conduct a feedback current resulting from the Miller-Effect.

5. The voltage regulator of claim 4 , further comprising a second resistor having a first end coupled to the output of the error amplifier and a second end coupled to the first end of the compensation capacitor, to cancel an effect of an output signal opposite in phase to an output signal of the error amplifier, resulting from a feed-forward current flowing in the compensation capacitor.

6. The voltage regulator of claim 1 , further comprising one or more devices coupled in series between the first output node and the second output node to ensure that a voltage at the second output node does not reach a same value as the supply voltage, when the external pass device is not coupled to the second output node.

7. The voltage regulator of claim 6 , wherein the one or more devices comprise one or more of:

diodes; or

diode-connected transistors.

8. A voltage regulator comprising:

a first output node configured to provide a regulated output voltage;

a second output node configured to couple to a control terminal of an external transistor device that has one end of its channel coupled to the first output node to provide a load current for high-voltage applications;

an internal transistor device having a first end of its channel coupled to a supply voltage and a second end of its channel coupled to the second output node to control the external transistor device;

a current branch configured to establish a current flowing in the internal transistor device;

an error amplifier having a first input configured to receive a reference signal and a second input coupled in a feedback loop with the first output node, and further having an output configured to control the current branch to control the regulated output voltage;

a load capacitor coupled between the first output node and reference ground; and

a first resistor configured to decouple the load capacitor from the second input of the error amplifier when the load current has a magnitude lower than a specified value.

9. The voltage regulator of claim 8 , further comprising a second resistor having a first end coupled to a first end of the first resistor, and a second end coupled to the second output node to create a bias current in the internal transistor device when the external pass device is not providing the load current.

10. The voltage regulator of claim 9 , further comprising a compensation capacitor having a first end coupled to the output of the error amplifier and a second end coupled to the second end of the channel of the internal transistor device, to conduct a feedback current resulting from the Miller-Effect.

11. The voltage regulator of claim 10 , further comprising a third resistor having a first end coupled to the output of the error amplifier and a second end coupled to the first end of the compensation capacitor, to cancel an effect of an output signal opposite in phase to an output signal of the error amplifier, resulting from a feed-forward current flowing in the compensation capacitor.

12. The voltage regulator of claim 11 , further comprising a fourth resistor having a first end coupled to the second end of the channel of the internal transistor device, and a second end coupled to the second output node to counter effects of negative impedance caused by a current-gain of the external transistor device at the control terminal of the external transistor device.

13. The voltage regulator of claim 12 , further comprising one or more diode devices coupled in series between the second end of the channel of the internal transistor device and the first end of the first resistor, to clamp the regulated output voltage.

14. The voltage regulator of claim 8 , wherein the current branch is a source follower stage comprising a current limiter configured to limit current flowing in the source follower stage.

15. The voltage regulator of claim 14 , wherein the source follower stage comprises a transistor device in a current mirror configuration with the internal transistor device, to mirror a multiple of the current flowing in the source-follower stage to the second node of the channel of the internal transistor device.

16. A method for regulating an output voltage at an output node configured in a feedback loop, the method comprising:

generating a first control signal based on a reference voltage and the output voltage;

using the first control signal to control a first current flowing in a first current branch;

mirroring a multiple of the first current to a first pass device to obtain a second current flowing in the first pass device to control the output voltage;

using a voltage developed by the second current to control a second pass device configured to provide a load current into the output node; and

decoupling a capacitor coupled between the output node and reference ground from the feedback loop when the load current has a magnitude lower than a specified value.

17. The method of claim 16 , further comprising creating a bias current in the first pass device when the second pass device is not providing the load current.

18. The method of claim 16 , further comprising eliminating effects of negative impedance caused by a current-gain of the second pass device at a control terminal of the second pass device.

19. A voltage regulator comprising:

a first output node configured to provide a regulated output voltage;

a second output node configured to couple to a control terminal of an external pass transistor that has its channel coupled between a supply voltage and the first output node, to provide a load current into the first output node;

a first resistor coupled between the second output node and a first internal node;

a second resistor coupled between the second output node and a second internal node;

a third resistor coupled between the second internal node and the first output node;

a load capacitor coupled between the first output node and reference ground;

an internal pass transistor having a channel coupled between the supply voltage and the first internal node;

a source-follower stage coupled between the supply voltage and reference ground, and configured to mirror a multiple of a current flowing in the source-follower stage to the internal pass transistor; and

an error amplifier having a first input configured to receive a reference signal and a second input coupled to the second internal node, and further having an output configured to control the source-follower stage to control the regulated output voltage.

20. The voltage regulator of claim 19 , further comprising a compensation capacitor and a fourth resistor coupled in series between the output of the error amplifier and the first internal node.

21. The voltage regulator of claim 20 , wherein a value of the fourth resistor is greater than a transconductance of the internal pass device.

22. The voltage regulator of claim 19 , further comprising one or more diode devices coupled between the first internal node and the second internal node.

23. A system comprising:

a voltage regulator comprising:

a first output node configured to provide a regulated output voltage;

a second output node;

a first resistor coupled between the second output node and a first internal node;

a second resistor coupled between the second output node and a second internal node;

a third resistor coupled between the second internal node and the first output node;

a load capacitor coupled between the first output node and reference ground;

an internal pass transistor having a channel coupled between the supply voltage and the first internal node;

a source-follower stage coupled between the supply voltage and reference ground, and configured to mirror a multiple of a current flowing in the source-follower stage to the internal pass transistor; and

an error amplifier having a first input configured to receive a reference signal and a second input coupled to the second internal node, and further having an output configured to control the source-follower stage to control the regulated output voltage;

an external pass transistor having a control terminal coupled to the second output node of the voltage regulator, and further having a its channel coupled between a supply voltage and the first output node of the voltage regulator, to provide a load current into the first output node of the voltage regulator; and

a load coupled to the first output node to conduct the load current.

24. The system of claim 23 , wherein the voltage regulator is configured on an integrated circuit.

25. The system of claim 23 , wherein the internal pass device is a MOSFET and the external pass transistor is a BJT.

26. A voltage regulator comprising:

a first node configured to provide a regulated output voltage;

a second node;

an internal pass device having a first end of its channel coupled to a supply voltage and a second end of its channel coupled to the second node;

a current branch coupled to the internal pass device;

an error amplifier having a first input configured to receive a reference signal and a second input coupled in a feedback loop with the first node, and further having an output configured to control the current branch to establish current flowing in the internal pass device, to control the regulated output voltage; and

a first resistor having a first end coupled to the first node and a second end coupled to the second node to establish a bias current in the internal pass device to provide a load current into the first node.

27. The voltage regulator of claim 26 , further comprising:

a load capacitor coupled between the first node and reference ground; and

a second resistor having one end coupled to the first node and a second end coupled to the first end of the first resistor, to decouple the load capacitor from the feedback loop when the load current has a magnitude lower than a specified value.

28. The voltage regulator of claim 26 further comprising a compensation capacitor having a first end coupled to the output of the error amplifier and a second end coupled to the second node, to conduct a feedback current resulting from the Miller-Effect.

29. The voltage regulator of claim 28 , further comprising a second resistor having a first end coupled to the output of the error amplifier and a second end coupled to the first end of the compensation capacitor, to cancel an effect of an output signal opposite in phase to an output signal of the error amplifier, resulting from a feed-forward current flowing in the compensation capacitor.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
MERGER Recorded Dec 11, 2017
From: STANDARD MICROSYSTEMS CORPORATION
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 044824/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2009
From: MCLEOD, SCOTT C.
To: STANDARD MICROSYSTEMS CORPORATION
Reel/Frame 022341/0488 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2009
From: PULIJALA, SRINIVAS K.
To: STANDARD MICROSYSTEMS CORPORATION
Reel/Frame 022289/0187 →