Scalable electrically eraseable and programmable memory (EEPROM) cell array
View Patent ↗A non-volatile memory (NVM) system includes a plurality of NVM cells fabricated in a dual-well structure. Each NVM cell includes an access transistor and an NVM transistor, wherein the access transistor has a drain region that is continuous with a source region of the NVM transistor. The drain regions of each NVM transistor in a column of the array are commonly connected to a corresponding bit line. The control gates of each NVM transistor in a row of the array are commonly connected to a corresponding word line. The source regions of each of the access transistors in the array are commonly coupled. The NVM cells are programmed and erased without having to apply the high programming voltage V PP across the gate dielectric layers of the access transistors. As a result, the NVM cells can be scaled down to sub-0.35 micron geometries.
1. A method of operating a non-volatile memory cell having an access transistor and a non-volatile memory transistor, the method comprising:
erasing the non-volatile memory cell by applying a first control voltage to a control gate of the non-volatile memory transistor, and applying a second control voltage to a well region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a first direction in the non-volatile memory transistor;
programming the non-volatile memory cell by applying the second control voltage to the control gate of the non-volatile memory transistor, and applying the first control voltage to the well region and a drain region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a second direction in the non-volatile memory transistor; and
reading the non-volatile memory cell by turning on the access transistor and monitoring a current flow through the non-volatile memory transistor and the access transistor;
maintaining a control gate of the access transistor at the second control voltage during the erase operation; and
maintaining the control gate of the access transistor at the first control voltage during the programming operation.
2. A method of operating a non-volatile memory cell having an access transistor and a non-volatile memory transistor, the method comprising:
erasing the non-volatile memory cell by applying a first control voltage to a control gate of the non-volatile memory transistor, and applying a second control voltage to a well region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a first direction in the non-volatile memory transistor;
programming the non-volatile memory cell by applying the second control voltage to the control gate of the non-volatile memory transistor, and applying the first control voltage to the well region and a drain region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a second direction in the non-volatile memory transistor; and
reading the non-volatile memory cell by turning on the access transistor and monitoring a current flow through the non-volatile memory transistor and the access transistor; and
maintaining a source of the access transistor in a floating state during the erase and program operations.
3. A method of operating a non-volatile memory cell having an access transistor and a non-volatile memory transistor, the method comprising:
erasing the non-volatile memory cell by applying a first control voltage to a control gate of the non-volatile memory transistor, and applying a second control voltage to a well region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a first direction in the non-volatile memory transistor;
programming the non-volatile memory cell by applying the second control voltage to the control gate of the non-volatile memory transistor, and applying the first control voltage to the well region and a drain region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a second direction in the non-volatile memory transistor;
reading the non-volatile memory cell by turning on the access transistor and monitoring a current flow through the non-volatile memory transistor and the access transistor; and
preventing erasing of the non-volatile memory cell by applying the second control voltage to the control gate of the non-volatile memory transistor, while the second control voltage is applied to the well region of the non-volatile memory transistor.
4. A method of operating a non-volatile memory cell having an access transistor and a non-volatile memory transistor, the method comprising:
erasing the non-volatile memory cell by applying a first control voltage to a control gate of the non-volatile memory transistor, and applying a second control voltage to a well region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a first direction in the non-volatile memory transistor;
programming the non-volatile memory cell by applying the second control voltage to the control gate of the non-volatile memory transistor, and applying the first control voltage to the well region and a drain region of the non-volatile memory transistor, wherein the first and second control voltages induce a tunneling current having a second direction in the non-volatile memory transistor;
reading the non-volatile memory cell by turning on the access transistor and monitoring a current flow through the non-volatile memory transistor and the access transistor; and
preventing programming of the non-volatile memory cell by applying an intermediate voltage, between the first control voltage and the second control voltage, to the drain of the non-volatile memory transistor, while the second control voltage is applied to the control gate of the non-volatile memory transistor.
5. A method of operating an array of non-volatile memory cells located in a well region, each having an access transistor and a non-volatile memory transistor, the method comprising:
erasing a non-volatile memory cell of the array by applying a first control voltage to a control gate of the non-volatile memory transistor of the non-volatile memory cell, and applying a second control voltage to the well region and to a control gate of each access transistor of the array, wherein the first and second control voltages induce a tunneling current having a first direction in the non-volatile memory transistor;
programming the non-volatile memory cell by applying the second control voltage to the control gate of the non-volatile memory transistor of the non-volatile memory cell, and applying the first control voltage to the well region, a drain region of the non-volatile memory transistor, and to the control gate of each access transistor of the array, wherein the first and second control voltages induce a tunneling current having a second direction in the non-volatile memory transistor.
6. The method of claim 5 , wherein the first and second control voltages induce Fowler-Nordheim tunneling in the non-volatile memory transistor during both the erasing and programming steps.
7. The method of claim 5 , further comprising maintaining a source region of each access transistor of the array in a floating state during the erasing and programming steps.
8. The method of claim 5 , wherein the first control voltage is ground, and the second control voltage is a positive voltage.
9. The method of claim 5 , further comprising applying a third control voltage, intermediate the first and second control voltages, to drain regions of one or more non-volatile memory transistors of the array during the programming step, thereby preventing programming of these one or more non-volatile memory transistors.
10. The method of claim 5 , further comprising applying the second control voltage to control gates of one or more non-volatile memory transistors of the array during the erase step, thereby preventing erasing of these one or more non-volatile memory transistors.
11. A method of operating an array of non-volatile memory cells located in a well region, each having an access transistor and a non-volatile memory transistor, the method comprising:
programming a first non-volatile memory cell in a first row of the array by applying a first control voltage to a control gate of the non-volatile memory transistor of the first non-volatile memory cell, and applying a second control voltage to the well region, to a drain region of the non-volatile memory transistor of the first non-volatile memory cell, and to a control gate of each access transistor of the array, wherein the first and second control voltages induce a tunneling current having a first direction in the first non-volatile memory transistor; and
while programming the first non-volatile memory cell, applying a third control voltage, intermediate the first and second control voltages, to a drain region of a non-volatile memory transistor of a second non-volatile memory cell in the first row of the array, thereby preventing programming of the non-volatile memory transistor of the second non-volatile memory cell.
12. The method of claim 11 , further comprising: while programming the first non-volatile memory cell, applying the second control voltage to control gates of a plurality of non-volatile memory transistors in a second row of the array, thereby preventing programming of the non-volatile memory transistors in the second row of the array.
13. The method of claim 11 , further comprising maintaining a source region of each access transistor of the array in a floating state while programming the first non-volatile memory cell.
14. The method of claim 11 , wherein the first control voltage is a positive voltage, and the second control voltage is ground.
15. The method of claim 11 , further comprising:
erasing the first and second non-volatile memory cells of the first row of the array by applying the second control voltage to the control gates of the non-volatile memory transistors of the first and second non-volatile memory cells, and applying the first control voltage to the well region and to a control gate of each access transistor of the array, wherein the first and second control voltages induce a tunneling current having a second direction in the non-volatile memory transistors of the first and second non-volatile memory cells.
16. The method of claim 15 , further comprising: while erasing the first and second non-volatile memory cells, applying the first control voltage to control gates of a plurality of non-volatile memory transistors in a second row of the array, thereby preventing erasing of the non-volatile memory transistors in the second row of the array.
17. The method of claim 15 , further comprising maintaining a source region of each access transistor of the array in a floating state while erasing the first and second non-volatile memory cells.
18. The method of claim 15 , further comprising maintaining a drain region of each non-volatile memory transistor of the array in a floating state while erasing the first and second non-volatile memory cells.
19. The method of claim 15 , wherein the first and second control voltages induce Fowler-Nordheim tunneling in the non-volatile memory transistor of the first non-volatile memory cell during both the erasing and programming steps.