Metal structure for memory device

1. A semiconductor device, comprising:

a substrate;

a static random access memory (SRAM) unit cell formed in the substrate;

a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell;

a second metal layer formed over the first metal layer, the second metal layer including:

a bit line and a complementary bit line each having a first thickness; and

a Vcc line disposed between the bit line and the complementary bit line; and

a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness, wherein the third metal layer further includes a first Vss line that continuously runs parallel with the word line from at least the bit line to at least the complementary bit line.

2. The semiconductor device of claim 1 , wherein a ratio of the second thickness to the first thickness is greater than 1.05.

3. The semiconductor device of claim 1 , wherein a ratio of the second thickness to the first thickness is greater than 1.15.

4. The semiconductor device of claim 1 , wherein the first Vss line is disposed between the word line and another word line of an adjacent SRAM unit cell.

5. The semiconductor device of claim 1 , further comprising a fourth metal layer formed over the third metal layer, wherein the fourth metal layer includes a second Vss line electrically coupled to the first Vss line.

6. The semiconductor device of claim 5 , wherein the first Vss line runs perpendicular to the second Vss line.

7. The semiconductor device of claim 1 , wherein the second metal layer has a greater thickness than the first metal layer.

8. The semiconductor device of claim 1 , wherein the SRAM unit cell is a 6T unit cell that includes:

two cross-coupled inverters having a first data storage node and a second data storage node, each inverter including a pull-down transistor and a pull-up transistor; and

first and second pass-gate transistors to control data read or data write functions.

9. The semiconductor device of claim 8 , wherein the SRAM unit cell further includes a plurality of other transistors for data storage and read/write functionality.

10. The semiconductor device of claim 1 , further comprising a fourth metal layer formed over the third metal layer, wherein the fourth metal layer has a greater thickness than the third metal layer such that a thickness ratio of the fourth metal layer to the third metal layer is greater than 1.1.

11. A memory device, comprising:

a memory unit cell formed in a substrate;

a first metal layer formed over the substrate, the first metal layer providing local interconnection to the memory unit cell;

a second metal layer formed over the first metal layer, the second metal layer including a first bit line, a second bit line, and a power supply line disposed between the first and second bit lines;

a third metal layer formed over the second metal layer, the third metal layer including a word line, wherein the third metal layer further includes a first Vss line that continuously extends parallel to the word line from at least the first bit line to at least the second bit line;

wherein a length ratio of the word line to the first bit line is greater than about 2.0 in the memory unit cell;

wherein the first bit line has a first resistance and the word line has a second resistance less than the first resistance.

12. The memory device of claim 11 , wherein the first bit line has a first thickness;

wherein the word line has a second thickness greater than the first thickness; and

wherein a thickness ratio of the second thickness to the first thickness is greater than 1.05.

13. The memory device of claim 11 , wherein the memory unit cell includes a SRAM memory unit cell.

14. The memory device of claim 13 , wherein the first Vss is disposed between the word line and another word line of an adjacent memory cell unit.

15. The memory device of claim 14 , further comprising a fourth metal layer formed over the third metal layer, wherein the fourth metal layer includes a second Vss line that is perpendicular to the first Vss line, the second Vss line being electrically coupled to the first Vss line.

16. A device, comprising:

a substrate;

a memory unit cell in the substrate;

a first metal layer over the substrate, the first metal layer providing local interconnection to the memory unit cell;

a second metal layer including a bit line, a complementary bit line, and a Vcc line disposed between the bit line and the complementary bit line, the bit line and the complementary bit line each having a first thickness;

a third metal layer over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness, wherein the third metal layer further includes a first Vss line that continuously extends parallel with the word line from at least the complementary bit line to at least the bit line; and

a fourth metal layer formed over the third metal layer, wherein the fourth metal layer has a greater thickness than the third metal layer such that a thickness ratio of the fourth metal layer to the third metal layer is greater than 1.1.

17. The device of claim 16 , wherein a thickness ratio of the second thickness to the first thickness is greater than 1.05.

18. The device of claim 16 , wherein the fourth metal layer includes a second Vss line electrically coupled to the first Vss line, the second Vss line perpendicular to the first Vss line.

19. The memory device of claim 16 , further comprising a fourth metal layer formed over the third metal layer, wherein the fourth metal layer has a greater thickness than the third metal layer such that a thickness ratio of the fourth metal layer to the third metal layer is greater than 1.1.