Fast common mode feedback control for differential driver
View Patent ↗A system and method for a fast stabilizing output buffer. A differential driver circuit is provided with an amplifier stage for receiving a differential input signal and generating a differential output based upon the input signal. The differential output has a corresponding common-mode (CM) voltage level typically based upon a value half of the power supply. A common-mode feedback buffer (CMFB) stage detects a change in the CM voltage level and recovers the CM voltage level to its desired value within a very fast settling time based upon a very high bus frequency. The CMFB stage utilizes a topology comprising only a single device. In one embodiment, this single device is a nmos transistor utilized as a transimpedance stage. Stability is provided by a circuit biasing stage and a shunting capacitor within the CMFB stage.
1. A differential driver circuit comprising:
a driver stage configured to generate a differential output with an associated predetermined common-mode (CM) voltage level at a CM node; and
a common-mode feedback buffer (CMFB) stage coupled to the driver stage, wherein the CMFB stage comprises a single transistor first stage;
wherein the first stage is configured to:
track voltage changes corresponding to the CM node with a gate terminal of the single transistor via a first resistor connected to the CM node and the gate terminal; and
recover via a drain terminal of the single transistor a voltage level at the CM node to the predetermined CM voltage level; and
wherein the CMFB stage is configured to cancel a pole formed by a gate-to-source parasitic capacitance of the single transistor with a capacitor shunting the first resistor.
2. The differential driver circuit as recited in claim 1 , wherein the single transistor is a transistor having:
a drain terminal coupled to an on-resistance of an input transistor within said driver stage, wherein the on-resistance is coupled to a second resistor coupled to said CM node; and
a source terminal coupled to a first steady-state reference level.
3. The differential driver circuit as recited in claim 1 , wherein the differential driver further comprises a bias stage comprising a replica transistor having a source terminal coupled to said first steady-state reference level, wherein the replica transistor has matching transistor characteristics of the single transistor.
4. The differential driver circuit as recited in claim 3 , wherein the bias stage further comprises circuitry for current sources configured to supply a greater amount of current to the single transistor than to said replica transistor.
5. The differential driver circuit as recited in claim 4 , wherein the bias stage is further configured to:
detect via said replica transistor and said current sources a predetermined current draw threshold by the CMFB stage; and
recover the CM node voltage level to the predetermined CM voltage level in response to detecting the predetermined current draw threshold.
6. The differential driver circuit as recited in claim 4 , wherein the bias stage further comprises circuitry for current sinks coupled to a second steady-state reference level with a same reference level value but a separate reference from said first steady-state reference level.
7. The differential driver circuit as recited in claim 4 , wherein the bias stage further comprises an output node for said circuitry connected to the first resistor and said gate terminal for adjusting current passing through the first resistor.
8. The differential driver circuit as recited in claim 7 , wherein the CMFB stage further comprises a third resistor between a first differential signal of said differential output and said CM node and the second resistor between said CM node and the drain terminal of said input transistor, wherein the third resistor has a same impedance as said second resistor.
9. A bus communication system comprising:
a transmitter configured to generate a differential output with an associated predetermined common-mode (CM) voltage level at a CM node;
a receiver configured to receive the differential output; and
a bus comprising one or more data lines coupling the differential output of the transmitter to the receiver; and
wherein the transmitter comprises a common-mode feedback buffer (CMFB) stage comprising a single transistor first stage;
wherein the first stage is configured to:
track voltage changes corresponding to the CM node with a gate terminal of the single transistor via a first resistor connected to the CM node and the gate terminal; and
recover via a drain terminal of the single transistor a voltage level at the CM node to the predetermined CM voltage level; and
wherein the CMFB stage is configured to cancel a pole formed by a gate-to-source parasitic capacitance of the single transistor with a capacitor shunting the first resistor.
10. The bus communication system as recited in claim 9 , wherein the single transistor is a transistor having:
a drain terminal coupled to an on-resistance of an input transistor within said driver stage, wherein the on-resistance is coupled to a second resistor coupled to said CM node; and
a source terminal coupled to a first steady-state reference level.
11. The bus communication system as recited in claim 9 , wherein the differential driver further comprises a bias stage comprising a replica transistor having a source terminal coupled to said first steady-state reference level, wherein the replica transistor has matching transistor characteristics of the single transistor.
12. The bus communication system as recited in claim 11 , wherein the bias stage further comprises circuitry for current sources configured to supply a greater amount of current to the single transistor said than to said replica transistor.
13. The bus communication system as recited in claim 12 , wherein the bias stage is further configured to:
detect via said replica transistor and said current sources a predetermined current draw threshold by the CMFB stage; and
recover the CM node voltage level to the predetermined CM voltage level in response to detecting the predetermined current draw threshold.
14. The bus communication system as recited in claim 12 , wherein the bias stage further comprises circuitry for current sinks coupled to a second steady-state reference level with a same reference level value but a separate reference from said first steady-state reference level.
15. The bus communication system as recited in claim 12 , wherein the bias stage further comprises an output node for said circuitry connected to the first resistor and said gate terminal for adjusting current passing through the first resistor.
16. The bus communication system as recited in claim 15 , wherein the CMFB stage further comprises a third resistor between a first differential signal of said differential output and said CM node and the second resistor between said CM node and the drain terminal of said input transistor, wherein the third resistor has a same impedance as said second resistor.
17. A differential signal driving method, the method comprising:
generating a differential output with an associated predetermined common-mode (CM) voltage level at a CM node;
tracking voltage changes corresponding to the CM node with a gate terminal of a single transistor via a first resistor connected to the CM node and the gate terminal, wherein the single transistor is in a single transistor first stage within a common-mode feedback buffer (CMFB); and
recovering via a drain terminal of the single transistor a voltage level at the CM node to the predetermined CM voltage level; and
canceling a pole formed by a gate-to-source parasitic capacitance of the single transistor with a capacitor shunting the first resistor.
18. The method as recited in claim 17 , wherein the single transistor is a transistor having:
a drain terminal coupled to an on-resistance of an input transistor within said driver stage, wherein the on-resistance is coupled to a second resistor coupled to said CM node; and
a source terminal coupled to a first steady-state reference level.
19. The method as recited in claim 18 , further comprising a replica transistor having a source terminal coupled to said first steady-state reference level, wherein the replica transistor has matching transistor characteristics of the single transistor.
20. The method as recited in claim 19 , further comprising supplying a greater amount of current to the single transistor than to said replica transistor.