Insulated gate semiconductor device and method for manufacturing the same
View Patent ↗A well region in which an insulated gate semiconductor element is formed is a diffusion region, and an impurity concentration of the well region is lower toward its bottom portion. This leads to a problem of increased resistance. Therefore, particularly, an insulated gate semiconductor element having an up-drain structure has a problem of increased on-resistance. A p type well region is formed by stacking two p type impurity regions on one another. The p type impurity regions are allowed to serve as the p type well region by sequentially stacking n type semiconductor layers, on one another, having p type impurities implanted into their surfaces and simultaneously diffusing the impurities by heat treatment. In this way, it is possible to obtain the p type well region in which an impurity concentration sufficient to secure a desired breakdown voltage is maintained approximately uniform up to a desired depth.
1. An insulated gate semiconductor device comprising:
a p type semiconductor substrate;
a first n type epitaxial semiconductor layer grown on the semiconductor substrate;
a second n type epitaxial semiconductor layer grown on the first n type semiconductor layer;
a third n type epitaxial semiconductor layer grown on the second n type semiconductor layer;
an n type impurity-diffusion region buried between the semiconductor substrate and the first n type semiconductor layer;
a first p type impurity-diffusion region buried between the first n type semiconductor layer and the second n type semiconductor layer;
a second p type impurity-diffusion region buried between the second n type semiconductor layer and the third n type semiconductor layer so as to be in contact with the first p type impurity-diffusion region;
a third p type impurity-diffusion region formed in the third n type semiconductor layer so as to be in contact with the second p type impurity region;
a region formed in the third p type impurity-diffusion region and comprising insulated gate semiconductor elements;
a conductive region formed in the second and third n type epitaxial semiconductor layers outside the second and third p type impurity-diffusion regions so as to reach the first p type impurity-diffusion region;
first and second electrodes connected to the region comprising insulated gate semiconductor elements; and
a third electrode connected to the conductive region.
2. The insulated gate semiconductor device of claim 1 , wherein the second and third p type impurity-diffusion regions each have an impurity concentration lower than an impurity concentration of the first p type impurity-diffusion region.
3. The insulated gate semiconductor device of claim 2 , wherein the second and third p type impurity-diffusion regions have the same impurity concentration.