IP Library Granted Patent US 8,154,048
Granted Patent B2
US 8,154,048 · App. 12/400,404 · Granted Apr 10, 2012

Diode with shortened reverse recovery time without reducing impurity concentration

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Quick Facts
Patent No.
US 8,154,048
App. No.
12/400,404
Granted
Apr 10, 2012
Kind
B2
Abstract

In a pn junction diode having a conductivity modulating element provided on a first principal surface of a semiconductor substrate, when an impurity concentration of a p type impurity region is lowered to shorten a reverse recovery time, hole injection is suppressed, thereby causing a problem that a forward voltage value is increased at a certain current point. Moreover, introduction of a life time killer to shorten the reverse recovery time leads to a problem of increased leak current. On an n− type semiconductor layer that is a single crystal silicon layer, a p type polycrystalline silicon layer (p type polysilicon layer) is provided. Since the polysilicon layer has more grain boundaries than the single crystal silicon layer, an amount of holes injected into the n− type semiconductor layer from the p type polysilicon layer in forward voltage application can be suppressed. Moreover, a natural oxide film formed between the n− type semiconductor layer and the p type polysilicon layer in formation of the p type polysilicon layer can also reduce the amount of holes injected into the n− type semiconductor layer. Thus, a time to extract the holes in reverse voltage application, that is, a reverse recovery time can be shortened without using a life time killer.

Claims (21)

1. A diode comprising:

an n type semiconductor silicon substrate having a top surface and a bottom surface;

an n type semiconductor layer disposed on the top surface of the n type semiconductor silicon substrate;

a p type polycrystalline silicon layer disposed on the n type semiconductor layer;

a first electrode disposed on the p type polycrystalline silicon layer so as to be in contact with the p type polycrystalline silicon layer;

a second electrode disposed on the bottom surface of the n type semiconductor substrate;

an oxide film disposed between the n type semiconductor layer and the p type polycrystalline silicon layer so that the oxide film is in contact with the n type semiconductor layer and the entire bottom surface of the p type polycrystalline layer; and

a high-concentration p type impurity region formed in a portion of the n type semiconductor layer that is below an edge portion of the p type polycrystalline silicon layer so as to have an impurity concentration higher than the p type polycrystalline silicon layer,

wherein the oxide film is in contact with the high-concentration p type impurity region.

2. The diode of claim 1 , wherein a thickness of the p type polycrystalline silicon layer is about 10 μm.

3. The diode of claim 1 , wherein an impurity concentration of the p type polycrystalline silicon layer is about 1×10 17 cm −3 .

4. The diode of claim 1 , wherein a thickness of the oxide film is about 1 Å to 100 Å.

5. The diode of claim 1 , wherein the p type polycrystalline silicon layer covers the entire portion of the n type semiconductor layer inside the high-concentration p type impurity region.

6. A diode comprising:

an n type semiconductor silicon substrate having a top surface and a bottom surface;

an n type semiconductor layer disposed on the top surface of the n type semiconductor silicon substrate;

a p type polycrystalline silicon layer disposed on the n type semiconductor layer;

a first electrode disposed on the p type polycrystalline silicon layer so as to be in contact with the p type polycrystalline silicon layer;

a second electrode disposed on the bottom surface of the n type semiconductor substrate;

an oxide film disposed between the n type semiconductor layer and the p type polycrystalline silicon layer so that the oxide film is in contact with the n type semiconductor layer and the entire bottom surface of the p type polycrystalline layer; and

a high-concentration p type impurity region formed in a portion of the n type semiconductor layer that is below an edge portion of the p type polycrystalline silicon layer so as to have an impurity concentration higher than the p type polycrystalline silicon layer, the high-concentration p type impurity region taking a rectangular shape in plan view of the diode.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →