Current sensing method and apparatus for a memory array
View Patent ↗A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.
1. In a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased, a method of sensing the data state of a selected memory cell comprising the steps of:
driving a selected word line to a selected word line bias voltage;
driving a selected bit line to a selected bit line bias voltage;
precharging a sense node to a precharge sense voltage;
summing, at the sense node, a selected bit line current and a reference current having a magnitude between the first and second nominal current levels; then
developing a voltage on the sense node that increases to a higher voltage for one data state, and decreases to a lower voltage for the other data state, while the selected bit line remains substantially at the selected bit line bias voltage; and
comparing the sense node voltage with a sense reference voltage to determine the selected memory cell data state.
2. The method as recited in claim 1 further comprising coupling a current flowing on the selected bit line to the sense node while the selected bit line remains substantially at the selected bit line bias voltage.
3. The method as recited in claim 1 wherein the precharge sense voltage is about the same as the sense reference voltage.
4. The method as recited in claim 1 wherein one of the selected bit line current and the reference current flows into the sense node, and the other of the selected bit line current and the reference current flows away from the sense node.
5. In a memory array having memory cells with diode-like conduction characteristics, for at least one of two memory cell data states, each memory cell coupled between a word line and a bit line and having first and second nominal current levels in accordance with its data state when forward biased, a method of sensing the data state of a selected memory cell comprising the steps of:
driving a selected word line from an unselected word line bias voltage to a selected word line bias voltage;
driving a selected bit line from an unselected bit line bias voltage to a selected bit line bias voltage; and
sensing current flow on the selected bit line while the selected bit line remains substantially at the selected bit line bias voltage to determine which of the first or second nominal current levels flows through the selected memory cell;
wherein the sensing current flow step comprises:
providing a noise detection line in the memory array associated with a group of bit lines, said noise detection line having capacitive coupling characteristics to adjoining structures matching those of each bit line of the group;
developing a reference current within the sensing circuit, said reference current having a magnitude between the first and second nominal current levels;
coupling any noise current received from the noise detection line into the reference current, resulting in a noise-adjusted reference current; and
subtracting the noise-adjusted reference current from the bit line current, resulting in a net bit line current; and
sensing whether the net bit line current is positive or negative.
6. The method defined by claim 5 wherein:
the selected bit line bias voltage differs from the unselected bit line bias voltage by at least about 1 volt.
7. The method defined by claim 5 further comprising:
the unselected word line bias voltage is close enough in magnitude to the selected bit line bias voltage so that current between the selected bit line and the unselected word lines is negligible relative to a selected memory cell current.
8. The method defined by claim 7 wherein:
the selected bit line bias voltage is about equal to the unselected word line bias voltage.
9. The method defined by claim 5 further comprising:
the unselected bit line bias voltage is close enough in magnitude to the selected word line bias voltage so that current between the selected word line and the unselected bit lines is negligible relative to a selected memory cell current.
10. The method defined by claim 9 wherein:
the unselected bit line bias voltage is about equal to the selected word line bias voltage.
11. The method defined by claim 5 wherein:
the selected word line bias voltage differs from the selected bit line bias voltage by at least about 1 volt.
12. The method defined by claim 5 wherein:
the memory array is a multi-level array having more than one plane of memory cells.
13. The method defined by claim 5 wherein:
the memory cells comprise antifuse memory cells.
14. The method defined by claim 5 wherein:
the selected word line bias voltage differs from the selected bit line bias voltage by at least about 1 volt;
the selected bit line bias voltage is about equal to the unselected word line bias voltage; and
the selected word line bias voltage is about equal to the unselected bit line bias voltage.
15. The method defined by claim 14 wherein:
the memory array is a multi-level array having more than one plane of memory cells.
16. The method defined by claim 15 wherein:
the memory cells comprise antifuse memory cells.
17. The method defined by claim 1 wherein:
the memory array is a multi-level array having more than one plane of memory cells.
18. The method defined by claim 1 wherein:
the memory cells comprise antifuse memory cells.