IP Library Granted Patent US 8,187,983
Granted Patent B2
US 8,187,983 · App. 12/424,726 · Granted May 29, 2012

Methods for fabricating semiconductor components using thinning and back side laser processing

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,187,983
App. No.
12/424,726
Granted
May 29, 2012
Kind
B2
Abstract

A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness; laser processing the back side of the thinned substrate to form at least one lasered feature on the back side; and dicing the substrate into a plurality of components having the lasered feature. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate. A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate.

Claims (31)

1. A method for fabricating a semiconductor component comprising:

providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side;

thinning the substrate from the back side to a selected thickness to form a thinned substrate having circuit side stresses generated by the integrated circuits and the circuitry; and

laser processing the back side of the thinned substrate to form a textured surface comprising a plurality of lasered features on the back side, with a location and a geometry of the lasered features selected to counteract bowing of the thinned substrate from the circuit side stresses.

2. The method of claim 1 wherein each lasered feature has an outside diameter of about 4-8 μm, a height of about 1-2 μm and a depth of about 0.25-1.0 μm.

3. The method of claim 1 further comprising following the thinning step performing additional back side processing on the back side of the thinned substrate.

4. The method of claim 1 wherein each lasered feature has a bell or hillock shape.

5. The method of claim 1 wherein the lasered features are formed in a plurality of separate patterns on the back side.

6. The method of claim 1 further comprising laser dicing the thinned substrate either prior to or after the laser processing step.

7. The method of claim 1 wherein the lasered features are configured to equalize the circuit side stresses the back side stresses.

8. A method for fabricating semiconductor components comprising:

providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side;

thinning the substrate from the back side to a selected thickness to form a thinned substrate having circuit side stresses generated by the integrated circuits and the circuity;

laser processing the back side to form a plurality of patterns of lasered features on the back side, with the patterns of lasered features located on the back side to generate back side stresses for counteracting bowing of the thinned substrate from the circuit side stresses; and

dicing the substrate into the semiconductor components with each component having at least one pattern of lasered features.

9. The method of claim of claim 8 wherein the substrate includes a plurality of edges and the patterns of lasered features are located parallel to the edges.

10. The method of claim 8 wherein the substrate includes a plurality of corners and the patterns of lasered features are located only in the corners.

11. The method of claim 8 wherein the substrate comprises a semiconductor wafer containing a plurality of semiconductor dice.

12. The method of claim 8 wherein the laser processing step is performed using a laser system configured to produce a laser beam comprising an expander configured to expand the laser beam, a lens system configured to redirect the laser beam, a diffractive optical element configured to separate the laser beam into a plurality of separate laser beams and a focusing device configured to focus the laser beam.

13. The method of claim 8 wherein each pattern comprises a parallel spaced array of ridges and grooves.

14. The method of claim 8 further comprising prior to the laser processing step performing additional back side processing on the back side of the substrate.

15. The method of claim 8 wherein the thinning step is performed using a method selected from the group consisting of mechanical planarization, chemical mechanical planarization and etching, and the selected thickness is less than 100 μm.

16. A method for fabricating semiconductor components comprising:

providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side;

providing a laser system configured to produce a laser beam comprising an expander configured to expand the laser beam, a lens system configured to redirect the laser beam, a diffractive optical element configured to separate the laser beam into a plurality of separate laser beams and a focusing device configured to focus the laser beam;

thinning the substrate from the back side to a selected thickness to form a thinned substrate having circuit side stresses generated by the integrated circuits and the circuitry;

selecting operational parameters of the laser system and laser processing the back side using the laser system and the operational parameters to form a plurality of lasered features on the back side configured to counteract bowing of the thinned substrate from the circuit side stresses; and

dicing the substrate into the semiconductor components.

17. The method of claim 16 wherein the lasered features are formed along parallel spaced scan lines.

18. The method of claim 17 wherein the scan lines are parallel to edges of the substrate.

19. The method of claim 18 wherein the laser system is also configured to perform the dicing step.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2009
From: WOOD, ALAN G.; CORBETT, TIM
To: MICRON TECHNOLOGY, INC.
Reel/Frame 022576/0866 →
Continuity (1)
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