DMOS transistor
View Patent ↗This invention provides a DMOS transistor that has a reduced ON resistance and is prevented from deterioration in strength against an electrostatic discharge. An edge portion of a source layer of the DMOS transistor is disposed so as to recede from an inner corner portion of a gate electrode. A silicide layer is structured so as not to extend out of the edge portion of the source layer. That is, although the silicide layer is formed on a surface of the source layer, the silicide layer is not formed on a surface of a portion of a body layer, which is exposed between the source layer and the inner corner portion of the gate electrode. As a result, the strength against the electrostatic discharge can be improved, because an electric current flows almost uniformly through whole of the DMOS transistor without converging.
1. A DMOS transistor comprising:
a semiconductor layer;
a body layer of a first general conductivity type formed in a surface portion of the semiconductor layer;
a source layer of a second general conductivity type formed in a surface portion of the body layer;
a silicide layer formed on the source layer; and
a gate electrode disposed on the semiconductor layer and having a shape of a closed loop so as to surround the body layer and the source layer in plan view of the transistor,
wherein the silicide layer is not formed in a space between the source layer and the gate electrode in the plan view.
2. The DMOS transistor of claim 1 , further comprising a silicidation prevention film covering the space between the source layer and the gate electrode so as to prevent formation of the silicide layer in the space.
3. The DMOS transistor of claim 2 , further comprising an electric field relaxing semiconductor layer of the first general conductivity type formed in the semiconductor layer adjacent an edge portion of the source layer.
4. The DMOS transistor of claim 3 , further comprising a gate insulation film and an electric field relaxing insulation film, wherein the gate electrode covers at least part of the gate insulation film and part of the electric field relaxing insulation film, and the electric field relaxing semiconductor layer is disposed below the electric field relaxing insulation film.
5. The DMOS transistor of claim 1 , further comprising an electric field relaxing semiconductor layer of the first general conductivity type formed in the semiconductor layer adjacent an edge portion of the source layer.
6. The DMOS transistor of claim 5 , further comprising a gate insulation film and an electric field relaxing insulation film, wherein the gate electrode covers at least part of the gate insulation film and part of the electric field relaxing insulation film, and the electric field relaxing semiconductor layer is disposed below the electric field relaxing insulation film.
7. A DMOS transistor comprising:
a semiconductor layer;
a body layer of a first general conductivity type formed in a surface portion of the semiconductor layer;
a source layer of a second general conductivity type formed in a surface portion of the body layer;
a silicide layer formed on the source layer; and
a gate electrode disposed on the semiconductor layer and having a shape of a closed loop so as to surround the body layer and the source layer in plan view of the transistor, the closed loop having an inner corner portion,
wherein there is a separation between the inner corner portion of the gate electrode and the source layer in the plan view, and
the silicide layer is not formed in an area of the semiconductor layer corresponding to the separation.
8. The DMOS transistor of claim 7 , further comprising a silicidation prevention film covering the area of the semiconductor layer corresponding to the separation so as to prevent formation of the silicide layer in the area.
9. The DMOS transistor of claim 8 , further comprising an electric field relaxing semiconductor layer of the first general conductivity type formed in the semiconductor layer adjacent the inner corner portion.
10. The DMOS transistor of claim 9 , further comprising a gate insulation film and an electric field relaxing insulation film, wherein the gate electrode extends to cover at least part of the gate insulation film and part of the electric field relaxing insulation film, and the electric field relaxing semiconductor layer is disposed below the electric field relaxing insulation film.
11. The DMOS transistor of claim 7 , further comprising an electric field relaxing semiconductor layer of the first general conductivity type formed in the semiconductor layer adjacent the inner corner portion.
12. The DMOS transistor of claim 11 , further comprising a gate insulation film and an electric field relaxing insulation film, wherein the gate electrode extends to cover at least part of the gate insulation film and part of the electric field relaxing insulation film, and the electric field relaxing semiconductor layer is disposed below the electric field relaxing insulation film.