IP Library Granted Patent US 8,475,673
Granted Patent B2
US 8,475,673 · App. 12/429,940 · Granted Jul 2, 2013

Method and apparatus for high aspect ratio dielectric etch

Inventor: Erik A. Edelberg (San Ramon, CA)
Assignee: Lam Research Company
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Quick Facts
Patent No.
US 8,475,673
App. No.
12/429,940
Granted
Jul 2, 2013
Kind
B2
Abstract

An apparatus for etching high aspect ratio features is provided. A plasma processing chamber is provided, comprising a chamber wall forming a plasma processing chamber enclosure, a lower electrode, an upper electrode, a gas inlet, and a gas outlet. A high frequency radio frequency (RF) power source is electrically connected to at least one of the upper electrode or lower electrode. A bias power system is electrically connected to both the upper electrode and the lower electrode, wherein the bias power system is able to provide a bias to the upper and lower electrodes with a magnitude of at least 500 volts, and wherein the bias to the lower electrode is pulsed to intermittently. A gas source is in fluid connection with the gas inlet. A controller is controllably connected to the gas source, the high frequency RF power source, and the bias power system.

Claims (25)

1. A method for etching high aspect ratio features in a dielectric layer over a substrate in a plasma processing chamber, comprising:

placing the substrate in the plasma processing chamber, with an upper electrode and a lower electrode, wherein the substrate is placed over the lower electrode, and wherein the upper electrode is space apart above the lower electrode and the substrate;

providing an etching gas into the plasma processing chamber;

forming a plasma in the plasma processing chamber, between the upper electrode and the lower electrode;

providing a bias to the upper electrode of at least 500 volts to provide secondary electrons with enough energy to pass through the plasma sheath to vias, wherein a positive charge at the bottom of the vias accelerates the secondary electrons to the bottom of the vias;

providing a pulsed bias of at least 500 volts to the lower electrode for etching the dielectric layer; and

wherein the forming a plasma in the plasma processing chamber, between the upper electrode and the lower electrode, comprises providing a high frequency RF with a frequency of over 10 MHz to at least one of the upper electrode or lower electrode.

2. The method, as recited in claim 1 , wherein the providing bias to the upper electrode comprises pulsing the bias to the upper electrode, so that bias is alternated between the upper electrode and the lower electrode.

3. The method, as recited in claim 2 , wherein the providing bias to the upper electrode, further comprise providing a low frequency RF power to the upper electrode, and wherein the providing bias to the lower electrode comprises providing a low frequency RF power to the lower electrode.

4. The method, as recited in claim 1 , wherein the providing bias to the upper electrode and providing bias to the lower electrode, comprises switching a bias between the upper electrode and lower electrode.

5. The method, as recited in claim 1 , wherein the providing the bias to the upper electrode accelerates ions into the upper electrode to generate the secondary electrons and accelerates the secondary electrons to bottoms of vias and wherein the providing a pulsed bias of at least 500 volts to the lower electrode is pulsed to collapse a generated plasma sheath.

6. The method, as recited in claim 5 , wherein the providing bias to the upper electrode and providing bias to the lower electrode are alternately switched a plurality of times, comprising switching a bias between the upper electrode and the lower electrode a plurality of times.

7. The method, as recited in claim 6 , wherein the providing bias to the lower electrode accelerates positive ions to bottoms of vias to provide etching of the vias, which creates a positive charge at bottoms of the vias, and wherein the secondary electrons reduce the positive charge at bottoms of the vias.

8. The method, as recited in claim 7 , wherein the high aspect ratio features have aspect ratios of at least 20-to-1.

9. The method, as recited in claim 1 , wherein the providing bias to the upper electrode and providing bias to the lower electrode are alternately switched a plurality of times, comprising switching a bias between the upper electrode and the lower electrode a plurality of times.

10. The method, as recited in claim 1 , wherein the providing bias to the lower electrode accelerates positive ions to bottoms of vias to provide etching of the vias, which creates a positive charge at bottoms of the vias, and wherein the secondary electrons reduce the positive charge at bottoms of the vias.

11. The method, as recited in claim 1 , wherein the high aspect ratio features have aspect ratios of at least 20-to-1.

12. The method, as recited in claim 1 , wherein providing the secondary electrons to the bottom of the vias reduces twisting that results from asymmetric etching.

13. A method for etching high aspect ratio features in a dielectric layer over a substrate in a plasma processing chamber, comprising:

placing the substrate in the plasma processing chamber, with an upper electrode and a lower electrode, wherein the substrate is placed over the lower electrode, and wherein the upper electrode is space apart above the lower electrode and the substrate;

providing an etching gas into the plasma processing chamber;

forming a plasma in the plasma processing chamber, between the upper electrode and the lower electrode;

providing a bias to the upper electrode of at least 500 volts to provide secondary electrons with enough energy to pass through a plasma sheath to vias, wherein a positive charge at the bottom of the vias accelerates the secondary electrons to the bottom of the vias;

providing a pulsed bias of at least 500 volts to the lower electrode for etching the dielectric layer, wherein the providing bias to the upper electrode and providing bias to the lower electrode, comprises switching a bias between the upper electrode and lower electrode, wherein the switch is performed at a frequency between 10 Hz to 100 kHz; and

wherein the forming a plasma in the plasma processing chamber, between the upper electrode and the lower electrode, comprises providing a high frequency RF with a frequency of over 10 MHz to at least one of the upper electrode or lower electrode.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2009
From: EDELBERG, ERIK A.
To: LAM RESEARCH CORPORATION
Reel/Frame 022999/0286 →
Continuity (1)
Related Publication 20100273332A1 · Oct 28, 2010