IP Library Granted Patent US 7,883,971
Granted Patent B2
US 7,883,971 · App. 12/431,391 · Granted Feb 8, 2011

Gate structure in a trench region of a semiconductor device and method for manufacturing the same

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Quick Facts
Patent No.
US 7,883,971
App. No.
12/431,391
Granted
Feb 8, 2011
Kind
B2
Abstract

Disclosed are a gate structure in a trench region of a semiconductor device and a method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Claims (48)

1. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming first and second drift regions in a semiconductor substrate;

forming an oxide layer on the substrate such that the oxide layer partially overlaps the first and second drift regions;

forming a trench between the first and second drift regions;

forming an oxide spacer on sidewalls of the trench;

forming an insulating layer at a bottom of the trench;

forming a gate in the trench and on the oxide layer;

forming a spacer on sidewalls of the gate; and

forming a source in one of the first and second drift regions and a drain in the other of the first and second drift regions.

2. The method according to claim 1 , wherein the step of forming the oxide layer includes:

forming a mask pattern on the substrate;

etching the substrate to a predetermined depth;

depositing the oxide layer over an entire surface of the semiconductor substrate; and

planarizing the oxide layer.

3. The method according to claim 1 , wherein the trench has a depth equal to or less than that of the first and second drift regions and a width equal to or less than a length of the oxide layer.

4. The method according to claim 3 , wherein the width of the trench is less than the length of the oxide layer.

5. The method according to claim 1 , wherein the spacer comprises silicon nitride.

6. The method according to claim 1 , wherein the first and second drift regions are symmetrical to and spaced apart from each other in a horizontal direction.

7. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming first and second drift regions in a semiconductor substrate;

forming an oxide layer on the substrate such that the oxide layer overlaps with each of the first and second drift regions;

forming a nitride layer on the substrate;

forming a trench between the first and second drift regions;

forming an oxide spacer on sidewalls of the trench;

forming an insulating layer at a bottom of the trench;

removing the nitride layer;

forming a gate in the trench region and at least partially on the oxide layer; and

forming a source in one of the first and second drift regions and a drain in the other of the first and second drift regions.

8. The method according to claim 7 , wherein the trench has a depth less than that of the first and second drift regions and a width less than a length of the oxide layer.

9. The method according to claim 7 , further comprising forming a nitride spacer on sidewalls of the gate.

10. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming first and second drift regions in a semiconductor substrate;

forming a mask pattern on the substrate;

etching the substrate to a predetermined depth;

depositing the oxide layer over an entire surface of the semiconductor substrate such that the oxide layer partially overlaps the first and second drift regions;

planarizing the oxide layer;

forming a trench between the first and second drift regions;

forming an oxide spacer on sidewalls of the trench;

forming an insulating layer at a bottom of the trench;

forming a gate in the trench and on the oxide layer; and

forming a source in one of the first and second drift regions and a drain in the other of the first and second drift regions.

11. The method according to claim 10 , wherein the oxide layer has a length greater than the distance between the first and second drift regions.

12. The method according to claim 10 , wherein the trench has (i) a depth equal to or less than that of the first and second drift regions and (ii) a width equal to or less than a length of the oxide layer.

13. The method according to claim 10 , wherein the width of the trench is less than the length of the oxide layer.

14. The method according to claim 10 , further comprising forming a nitride layer on the substrate prior to forming the trench between the first and second drift regions.

15. The method according to claim 14 , further comprising removing the nitride layer after forming the insulating layer at the bottom of the trench.

16. The method according to claim 10 , further comprising forming a nitride spacer on sidewalls of the gate.

17. The method according to claim 10 , wherein the first and second drift regions are symmetrical to and spaced apart from each other in a horizontal direction.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2019
From: DB HITEK CO., LTD.
To: COLUMBA TECHNOLOGIES INC.
Reel/Frame 049709/0857 →
CHANGE OF NAME Recorded Nov 30, 2017
From: DONGBU HITEK CO., LTD.
To: DB HITEK CO., LTD
Reel/Frame 044555/0913 →
MERGER AND CHANGE OF NAME Recorded Nov 29, 2017
From: DONGBU ELECTRONICS CO., LTD.; DONGBU HITEK CO., LTD.
To: DONGBU HITEK CO., LTD.
Reel/Frame 044533/0523 →