Charge trap type non-volatile memory device and method for fabricating the same

1. A charge trap type non-volatile memory device, comprising:

a tunnel insulation layer formed over a substrate;

a charge trap layer formed over the tunnel insulation layer, the charge trap layer including a charge trap polysilicon thin layer and a charge trap nitride-based layer;

a charge barrier layer formed over the charge trap layer;

a gate electrode formed over the charge barrier layer; and

an oxide-based spacer directly contacting with sidewalls of the charge trap layer and provided to isolate the charge trap layer,

wherein

a thickness of the charge trap polysilicon thin layer is smaller than a thickness of the charge trap nitride-based layer,

the charge trap polysilicon thin layer has a recess portion,

the oxide-based spacer formed over the sidewalls of the charge trap layer extends inwardly to the recess portion of the charge trap polysilicon thin layer, and

a lower surface of the charge trap nitride-based layer exposed by the recess portion slopes towards the charge trap polysilicon thin layer.

2. The charge trap type non-volatile memory device of claim 1 , wherein the oxide-based spacer is formed by performing an oxidation process on the charge trap layer.

3. The charge trap type non-volatile memory device of claim 1 , wherein the charge trap layer comprises a stack structure of the charge trap polysilicon thin layer and the charge trap nitride-based layer.

4. The charge trap type non-volatile memory device of claim 3 , wherein the charge trap nitride-based layer comprises:

a first nitride-based layer formed over the charge trap polysilicon thin layer; and

a second nitride-based layer formed over the first nitride-based layer and having a higher nitrogen content than the first nitride-based layer.

5. The charge trap type non-volatile memory device of claim 4 , wherein the second nitride-based layer is formed to have a ratio of silicon (Si) to nitrogen (N) ranging approximately 1:1.33-2.0.

6. The charge trap type non-volatile memory device of claim 1 , wherein the charge trap polysilicon thin layer is formed to a thickness ranging from approximately 10 Å to approximately 30 Å.

7. The charge trap type non-volatile memory device of claim 1 , wherein the charge trap nitride-based layer is formed to have a ratio of Si to N ranging approximately 1:1.30-1.36.

8. The charge trap type non-volatile memory device of claim 1 , wherein the oxide-based spacer directly contacts with the sloped lower surface of the charge trap nitride-based layer and the recess portion of the charge trap polysilicon thin layer.