Nonvolatile memory devices having electromagnetically shielding source plates

1. A non-volatile memory device, comprising:

a memory array comprising a plurality of strings of non-volatile memory cells located at side-by-side locations in a substrate, said plurality of strings of non-volatile memory cells comprising a row of ground select transistors;

a plurality of bit lines electrically coupled to respective ones of the plurality of strings of non-volatile memory cells; and

a source plate electrically coupled to source regions of the row of ground select transistors, said source plate extending in two-dimensions over a plurality of word lines associated with each of the plurality of strings of non-volatile memory cells.

2. The non-volatile memory device of claim 1 , wherein said source plate extends as an uninterrupted layer across a plurality of rows of the plurality of strings of non-volatile memory cells.

3. The non-volatile memory device of claim 2 , wherein said source plate extends between said plurality of bit lines and said plurality of strings of non-volatile memory cells.

4. The non-volatile memory device of claim 3 , wherein each of the plurality of strings of non-volatile memory cells comprises a string select transistor having a drain region in the substrate; and wherein each of said plurality of bit lines is electrically coupled to a corresponding drain region of a string select transistor.

5. The non-volatile memory device of claim 1 , wherein each of the plurality of strings of non-volatile memory cells comprises a string select transistor having a drain region in the substrate; and wherein each of said plurality of bit lines is electrically coupled to a corresponding drain region of a string select transistor.

6. The non-volatile memory device of claim 4 , further comprising a source line electrically coupled by a source line plug to said source plate; and wherein said source line is coplanar with said plurality of bit lines.

7. The non-volatile memory device of claim 1 , wherein each of the plurality of strings of non-volatile memory cells comprises a string select transistor having a drain region in the substrate; and wherein each of said plurality of bit lines is electrically coupled by a bit line plug to a corresponding drain region of a string select transistor.

8. The non-volatile memory device of claim 7 , further comprising a diffusion barrier layer surrounding each of a plurality of the bit line plugs; and wherein the diffusion barrier layer is coplanar with said source plate.

9. The non-volatile memory device of claim 8 , wherein the diffusion barrier layer comprises an electrically insulating material selected from a group consisting of silicon nitride and silicon oxynitride.

10. An integrated circuit memory device, comprising:

a non-volatile memory array comprising a plurality of NAND-type strings of non-volatile memory cells having respective ground select transistors and string select transistors therein;

a source plate extending over the plurality of NAND-type strings of non-volatile memory cells, said source plate electrically coupled to source terminals of each of the ground select transistors; and

a plurality of bit lines extending over said source plate, said plurality of bit lines electrically coupled to drain terminals of each of the string select transistors.

11. The memory device of claim 10 , wherein said source plate is configured as a continuous metal layer that operates to electromagnetically shield the non-volatile memory cells from fluctuations in voltages on said plurality of bit lines during memory programming operations.

12. A semiconductor device comprising:

a semiconductor substrate including a cell array region;

memory cell transistors disposed at the cell array region;

bitlines disposed on the memory cell transistors; and

a source plate disposed between the memory cell transistors and the bitlines to veil the memory cell transistors thereunder.

13. The semiconductor device as set forth in claim 12 , wherein the cell array region include parallel active regions each including a source region where a source electrode is formed, a drain region where a drain electrode is formed, and a plurality of cell regions between the source region and the drain region; and

wherein the source plate has an opening formed over the drain region and, except the opening, the entire surface of the cell array region is covered with the source plate.

14. The semiconductor device as set forth in claim 13 , further comprising:

a bitline plug penetrating the source plate through the opening to connect the bitline with the drain electrode.

15. The semiconductor device as set forth in claim 14 , further comprising:

a diffusion barrier layer disposed between the source plate and the bitline plug.

16. The semiconductor device as set forth in claim 13 , further comprising:

a common source line disposed below the source plate to electrically connect the source electrodes with one another,

wherein the source plate is electrically connected with the common source line.

17. The semiconductor device as set forth in claim 13 , wherein the source plate extends toward the source regions to be used as a common source line connecting electrically the source electrodes with one another.

18. The semiconductor device as set forth in claim 13 , further comprising:

pads spaced apart from the source plate and disposed in the opening,

wherein height, thickness, material of the pads are substantially identical to those of the source plate.

19. The semiconductor device as set forth in claim 12 , wherein the memory cell transistors are non-volatile memory transistors constituting a NAND memory cell string.

20. The semiconductor device as set forth in claim 19 , wherein each of the memory cell transistors is either one of a charge trap type non-volatile memory transistor and a floating gate type memory transistor.