In-package microelectronic apparatus, and methods of using same
A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s.
1. An apparatus comprising:
a mounting substrate for a processor, wherein the mounting substrate includes a die side and a land side;
a processor footprint configured on the mounting substrate die side, wherein the processor footprint is coupled to at least one processor interconnect;
a microelectonic die embedded in the mounting substrate, wherein the microelectronic die is coupled to the at least one processor interconnect, wherein the mounting substrate includes a core and a build-up layer, wherein the microelectronic die is a first memory die, the apparatus further including;
a subsequent microelectronic die, wherein the subsequent microelectronic die is also embedded in the mounting substrate, wherein the first memory die and the subsequent microelectronic die are vertically stacked, and wherein the subsequent microelectronic die is at least partially embedded in the build-up layer.
2. An apparatus comprising:
a mounting substrate for a processor, wherein the mounting substrate includes a die side and a land side;
a processor footprint configured on the mounting substrate die side, wherein the processor footprint is coupled to at least one processor interconnect;
a microelectonic die embedded in the mounting substrate, wherein the microelectronic die is coupled to the at least one processor interconnect, wherein the mounting substrate includes a core and a build-up layer, wherein the mounting substrate includes a core and a build-up layer, wherein the microelectronic die is a first memory die, the apparatus further including;
a subsequent memory die, wherein the subsequent memory die is also embedded in the mounting substrate, wherein the first memory die and the subsequent memory die are vertically stacked, and wherein the subsequent memory die is at least partially embedded in the build-up layer.