Granted Patent B2

US 7,830,739 · App. 12/457,962 · Granted Nov 9, 2010

Abstract

Claims (17)

1. A semiconductor memory device in which a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines, comprising:

a plurality of unit blocks connected in cascade into which the memory cell array is divided;

a plurality of rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in said unit block and each including a plurality of sense amplifiers for amplifying data of the memory cells for each bit line pair;

first switch means for switching a connection state between said unit block and said row of sense amplifiers attached to said unit block;

two cache memories for storing two said rows of sense amplifiers attached to one of said unit blocks;

second switch means for switching a connection state between unshared rows of sense amplifiers attached only to said unit block located at both ends of the memory cell array and said cache memories; and

control means for controlling said first switch means and said second switch means so as to form a transfer path from said row of sense amplifiers attached to a predetermined said unit block leading to said cache memory using the plurality of bit lines, and for performing a transfer operation of data in said row of sense amplifier to said cache memory through the transfer path.

2. The semiconductor memory device according to claim 1 , wherein said control means transfers data in said row of sense amplifiers attached to said unit block to be refreshed, thereafter performs a refresh operation for said unit block to be refreshed using said row of sense amplifiers as a transfer source.

3. The semiconductor memory device according to claim 1 , wherein the memory cell array is configured by connecting N (N is an integer larger than or equal to 2) said unit blocks in cascade, and has N−1 said rows of sense amplifiers shared by two adjacent said unit blocks and two unshared said rows of sense amplifiers attached only to said unit blocks located at both ends of the memory cell array,

and wherein one said cache memory is arranged at one end of the memory cell array and the other said cache memory is arranged at the other end of the memory cell array.

4. The semiconductor memory device according to claim 1 , wherein an operation circuit for performing an operation using stored data in said cache memory is attached to each of said cache memories.

5. A semiconductor memory device in which a memory cell array including a plurality of memory cells formed at intersections between a plurality of word lines and a plurality of bit lines, comprising:

a plurality of unit blocks into which the memory cell array is divided;

a plurality of rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in said unit block and each including a plurality of sense amplifiers for amplifying data of the memory cells for each bit line pair;

switch means for switching a connection state between said unit block and said row of sense amplifiers attached to said unit block; and

control means for controlling said switch means so as to form a transfer path from said row of sense amplifiers as a transfer source attached to a predetermined said unit block leading to said row of sense amplifiers as a transfer destination not attached to the predetermined said unit block using the plurality of bit lines, and controls so that data of the transfer source is transferred to said row of sense amplifiers as the transfer destination.

6. The semiconductor memory device according to claim 5 , wherein said memory cell array is configured using a shared sense amplifier scheme in which adjacent said unit blocks share said row of sense amplifiers arranged therebetween.

Assignments (8)